SAA7104E Datasheet, PDF (3/70 Pages) NXP Semiconductors – Digital video encoder

Philips Semiconductors
Digital video encoder
Product specification
SAA7104E; SAA7105E
1 FEATURES
• Digital PAL/NTSC encoder with integrated high quality
scaler and anti-flicker filter for TV output from a PC
• Supports Intel® Digital Video Out (DVO) low voltage
interfacing to graphics controller
• 27 MHz crystal-stable subcarrier generation
• Maximum graphics pixel clock 85 MHz at double edged
clocking, synthesized on-chip or from external source
• Programmable assignment of clock edge to bytes (in
double edged mode)
• Synthesizable pixel clock (PIXCLK) with minimized
output jitter, can be used as reference clock for the VGC,
as well)
• PIXCLK output and bi-phase PIXCLK input (VGC clock
loop-through possible)
• Hot-plug detection through dedicated interrupt pin
• Supported VGA resolutions for PAL or NTSC legacy
video output up to 1280 × 1024 graphics data at
60 or 50 Hz frame rate
• Supported VGA resolutions for HDTV output up to
1920 × 1080 interlaced graphics data at 60 or 50 Hz
frame rate
• Three Digital-to-Analog Converters (DACs) for CVBS
(BLUE, C_B), VBS (GREEN, CVBS) and C (RED, C_R) at
27 MHz sample rate (signals in parenthesis are
optionally), all at 10-bit resolution
• Non-interlaced C_B-Y-C_R or RGB input at maximum
4 : 4 : 4 sampling
• Downscaling and upscaling from 50 to 400%
• Optional interlaced C_B-Y-C_R input of Digital Versatile
Disk (DVD) signals
• Optional non-interlaced RGB output to drive second
VGA monitor (bypass mode, maximum 85 MHz)
• 3 × 256 bytes RGB Look-Up Table (LUT)
• Support for hardware cursor
• HDTV up to 1920 × 1080 interlaced and 1280 × 720
progressive, including 3-level sync pulses
• Programmable border colour of underscan area
• Programmable 5 line anti-flicker filter
• On-chip 27 MHz crystal oscillator (3rd-harmonic or
fundamental 27 MHz crystal)
• Fast I²C-bus control port (400 kHz)
• Encoder can be master or slave
• Adjustable output levels for the DACs
• Programmable horizontal and vertical input
synchronization phase
• Programmable horizontal sync output phase
• Internal Colour Bar Generator (CBG)
• Optional support of various Vertical Blanking Interval
(VBI) data insertion
• Macrovision™⁽¹⁾ Pay-per-View copy protection system
rev. 7.01, rev. 6.1 and rev. 1.03 (525p) as option; this
applies to the SAA7104E only. The device is protected
by USA patent numbers 4631603, 4577216 and
4819098 and other intellectual property rights. Use of
the Macrovision anti-copy process in the device is
licensed for non-commercial home use only. Reverse
engineering or disassembly is prohibited. Please
contact your nearest Philips Semiconductors sales
office for more information.
• Optional cross-colour reduction for PAL and NTSC
CVBS outputs
• Power-save modes
• Joint Test Action Group (JTAG) boundary scan test
• Monolithic CMOS 3.3 V device, 5 V tolerant I/Os.
(1) Macrovision™ is a trademark of the Macrovision Corporation.
2004 Mar 04
3