SAA7104E Datasheet, PDF (43/70 Pages) NXP Semiconductors – Digital video encoder

Philips Semiconductors
Digital video encoder
Product specification
SAA7104E; SAA7105E
Table 79 Subaddress 97H
DATA BYTE
HFS
LOGIC
LEVEL
0
1
VFS
0
1
OFS
0
1
PFS
0
1
OVS
0
1
PVS
0
1
OHS
0
1
PHS
0
1
DESCRIPTION
horizontal sync is directly derived from input signal (slave mode) at pin HSVGC
horizontal sync is derived from a frame sync signal (slave mode) at pin FSVGC (only if
EFS is set HIGH)
vertical sync (field sync) is directly derived from input signal (slave mode) at
pin VSVGC
vertical sync (field sync) is derived from a frame sync signal (slave mode) at
pin FSVGC (only if EFS is set HIGH)
pin FSVGC is switched to input
pin FSVGC is switched to active output
polarity of signal at pin FSVGC in output mode (master mode) is active HIGH; rising
edge of the input signal is used in slave mode
polarity of signal at pin FSVGC in output mode (master mode) is active LOW; falling
edge of the input signal is used in slave mode
pin VSVGC is switched to input
pin VSVGC is switched to active output
polarity of signal at pin VSVGC in output mode (master mode) is active HIGH; rising
edge of the input signal is used in slave mode
polarity of signal at pin VSVGC in output mode (master mode) is active LOW; falling
edge of the input signal is used in slave mode
pin HSVGC is switched to input
pin HSVGC is switched to active output
polarity of signal at pin HSVGC in output mode (master mode) is active HIGH; rising
edge of the input signal is used in slave mode
polarity of signal at pin HSVGC in output mode (master mode) is active LOW; falling
edge of the input signal is used in slave mode
Table 80 Subaddresses 98H and 99H
DATA BYTE
DESCRIPTION
HLEN
horizontal length; HLEN = ^{n----u---m-----b----e---r---l-o-i-n-f--e-P----I--X----C----L----K----s-} – 1
Table 81 Subaddress 99H
DATA BYTE
DESCRIPTION
IDEL
input delay; defines the distance in PIXCLKs between the active edge of CBO and the first received
valid pixel
2004 Mar 04
43