SAA7104E Datasheet, PDF (13/70 Pages) NXP Semiconductors – Digital video encoder

Philips Semiconductors
Digital video encoder
Product specification
SAA7104E; SAA7105E
The internal clock can be switched completely to the pixel
clock input. In this event, the input FIFO is useless and will
be bypassed.
The entire pixel clock generation can be locked to the
vertical frequency. Both pixel clock dividers get
re-initialized every field. Optionally, the DTO can be
cleared with each V-sync. At proper programming, this will
make the pixel clock frequency a precise multiple of the
vertical and horizontal frequencies. This is required for
some graphic controllers.
7.11 Low-pass Clock Generation Circuit (CGC)
This block reduces the phase jitter of the synthesized pixel
clock. It works as a tracking filter for all relevant
synthesized pixel clock frequencies.
7.12 Encoder
7.12.1 VIDEO PATH
The encoder generates luminance and colour subcarrier
output signals from the Y, C_B and C_R baseband signals,
which are suitable for use as CVBS or separate Y and C
signals.
Input to the encoder, at 27 MHz clock (e.g. DVD), is either
originated from computer graphics at pixel clock, fed
through the FIFO and border generator, or a ITU-R BT.656
style signal.
Luminance is modified in gain and in offset (the offset is
programmable in a certain range to enable different black
level set-ups). A blanking level can be set after insertion of
a fixed synchronization pulse tip level, in accordance with
standard composite synchronization schemes. Other
manipulations used for the Macrovision anti-taping
process, such as additional insertion of AGC super-white
pulses (programmable in height), are supported by the
SAA7104E only.
To enable easy analog post filtering, luminance is
interpolated from a 13.5 MHz data rate to a 27 MHz data
rate, thereby providing luminance in a 10-bit resolution.
The transfer characteristics of the luminance interpolation
filter are illustrated in Figs 6 and 7. Appropriate transients
at start/end of active video and for synchronization pulses
are ensured.
Chrominance is modified in gain (programmable
separately for C_B and C_R), and a standard dependent
burst is inserted, before baseband colour signals are
interpolated from a 6.75 MHz data rate to a 27 MHz data
rate. One of the interpolation stages can be bypassed,
thus providing a higher colour bandwidth, which can be
used for the Y and C output.
The transfer characteristics of the chrominance
interpolation filter are illustrated in Figs 4 and 5.
The amplitude (beginning and ending) of the inserted
burst, is programmable in a certain range that is suitable
for standard signals and for special effects. After the
succeeding quadrature modulator, colour is provided on
the subcarrier in 10-bit resolution.
The numeric ratio between the Y and C outputs is in
accordance with the standards.
7.12.2 TELETEXT INSERTION AND ENCODING (NOT
SIMULTANEOUSLY WITH REAL-TIME CONTROL)
Pin TTX_SRES receives a WST or NABTS teletext
bitstream sampled at the crystal clock. At each rising edge
of the output signal (TTXRQ) a single teletext bit has to be
provided after a programmable delay at input pin
TTX_SRES.
Phase variant interpolation is achieved on this bitstream in
the internal teletext encoder, providing sufficient small
phase jitter on the output text lines.
TTXRQ_XCLKO2 provides a fully programmable request
signal to the teletext source, indicating the insertion period
of bitstream at lines which can be selected independently
for both fields. The internal insertion window for text is set
to 360 (PAL WST), 296 (NTSC WST) or 288 (NABTS)
teletext bits including clock run-in bits. The protocol and
timing are illustrated in Fig.14.
Alternatively, this pin can be provided with a buffered
crystal clock (XCLK) of 13.5 MHz.
7.12.3 VIDEO PROGRAMMING SYSTEM (VPS) ENCODING
Five bytes of VPS information can be loaded via the
I²C-bus and will be encoded in the appropriate format into
line 16.
7.12.4 CLOSED CAPTION ENCODER
Using this circuit, data in accordance with the specification
of Closed Caption or extended data service, delivered by
the control interface, can be encoded (line 21). Two
dedicated pairs of bytes (two bytes per field), each pair
preceded by run-in clocks and framing code, are possible.
The actual line number in which data is to be encoded, can
be modified in a certain range.
The data clock frequency is in accordance with the
definition for NTSC M standard 32 times horizontal line
frequency.
2004 Mar 04
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