SAA7104E Datasheet, PDF (47/70 Pages) NXP Semiconductors – Digital video encoder

Philips Semiconductors
Digital video encoder
Product specification
SAA7104E; SAA7105E
Table 100 Subaddresses DAH and DBH
DATA BYTE
DESCRIPTION
HTY
vertical trigger phase for the HD sync engine in input lines
Table 101 Subaddress DCH
DATA BYTE
HDSYE
HDTC
HDGY
HDIP
LOGIC
LEVEL
DESCRIPTION
0 the HD sync engine is off; default after reset
1 the HD sync engine is active
0 HD output path processes RGB; default after reset
1 HD output path processes YUV
0 gain in the HD output path is reduced, insertion of sync pulses is possible; default after
reset
1 full level swing at the input causes full level swing at the DACs in HD mode
0 interpolator for the colour difference signal in the HD output path is active; default after reset
1 interpolator for the colour difference signals in the HD output path is off
Table 102 Subaddresses F0H to F2H
DATA BYTE
DESCRIPTION
CC1R, CC1G RED, GREEN and BLUE portion of first cursor colour
and CC1B
Table 103 Subaddresses F3H to F5H
DATA BYTE
DESCRIPTION
CC2R, CC2G RED, GREEN and BLUE portion of second cursor colour
and CC2B
Table 104 Subaddresses F6H to F8H
DATA BYTE
DESCRIPTION
AUXR, AUXG RED, GREEN and BLUE portion of auxiliary cursor colour
and AUXB
Table 105 Subaddresses F9H and FAH
DATA BYTE
XCP
horizontal cursor position
DESCRIPTION
Table 106 Subaddress FAH
DATA BYTE
XHS
horizontal hot spot of cursor
DESCRIPTION
2004 Mar 04
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