SAA7104E Datasheet, PDF (19/70 Pages) NXP Semiconductors – Digital video encoder

Philips Semiconductors
Digital video encoder
Product specification
SAA7104E; SAA7105E
The following Sections give the set of equations required
to program the IC for the most common application: A post
processor in master mode with non-interlaced video input
data.
Some variables are defined below:
• InPix: the number of active pixels per input line
• InPpl: the length of the entire input line in pixel clocks
• InLin: the number of active lines per input field/frame
• TPclk: the pixel clock period
• RiePclk: the ratio of internal to external pixel clock
• OutPix: the number of active pixels per output line
• OutLin: the number of active lines per output field
• TXclk: the encoder clock period (37.037 ns).
7.20.1 TV DISPLAY WINDOW
At 60 Hz, the first visible pixel has the index 256,
710 pixels can be encoded; at 50 Hz, the index is 284,
702 pixels can be visible.
The output lines should be centred on the screen. It should
be noted that the encoder has 2 clocks per pixel;
see Table 59.
ADWHS = 256 + 710 − OutPix (60 Hz);
ADWHS = 284 + 702 − OutPix (50 Hz);
ADWHE = ADWHS + OutPix × 2 (all frequencies)
For vertical, the procedure is the same. At 60 Hz, the first
line with video information is number 19, 240 lines can be
active. For 50 Hz, the numbers are 23 and 287;
see Table 65.
FAL = 19 + ^{2----4---0-----–}----2-O----u----t-L----i-n-- (60 Hz);
FAL = 23 + ^{2----8---7-----–}----2-O----u----t-L----i-n-- (50 Hz);
LAL = FAL + OutLin (all frequencies)
Most TV sets use overscan, and not all pixels respectively
lines are visible. There is no standard for the factor, it is
highly recommended to make the number of output pixels
and lines adjustable. A reasonable underscan factor is
10%, giving approximately 640 output pixels per line.
7.20.2 INPUT FRAME AND PIXEL CLOCK
The total number of pixel clocks per line and the input
horizontal offset need to be chosen next. The only
constraint is that the horizontal blanking has at least
10 clock pulses.
The required pixel clock frequency can be determined in
the following way: Due to the limited internal FIFO size, the
input path has to provide all pixels in the same time frame
as the encoders vertical active time. The scaler also has to
process the first and last border lines for the anti-flicker
function. Thus:
TPclk = -----------------2---6---2----.-5-----^×-----1----7---1----6----^×-----T----X----c---l-k----------------- (60 Hz)
InPpl × integer_^{I--n-O---L--u-i-n-t--L--+}-i-n---2-- × 262.5_
TPclk = -----------------3---1---2----.-5-----^×-----1----7---2----8----^×-----T----X----c---l-k----------------- (50 Hz)
InPpl × integer_^{I--n-O---L--u-i-n-t--L--+}-i-n---2-- × 312.5_
and for the pixel clock generator
PCL = ^{TT----XP----cc---ll--kk-} × 2^{20 + PCLE} (all frequencies);
see Tables 68, 70 and 71. The divider PCLE should be set
according to Table 70. PCLI may be set to a lower or the
same value. Setting a lower value means that the internal
pixel clock is higher and the data get sampled up. The
difference may be 1 at 640 × 480 pixels resolution and 2 at
resolutions with 320 pixels per line as a rule of thumb. This
allows horizontal upscaling by a maximum factor of 2
respectively 4 (this is the parameter RiePclk).
PCLI = PCLE – ^{l--o---g----lR-o---i-g-e---2P----c---l--k-} (all frequencies)
The equations ensure that the last line of the field has the
full number of clock cycles. Many graphic controllers
require this. Note that the bit PCLSY needs to be set to
ensure that there is not even a fraction of a clock left at the
end of the field.
7.20.3 HORIZONTAL SCALER
XOFS can be chosen arbitrarily, the condition being that
XOFS + XPIX ≤ HLEN is fulfilled. Values given by the
VESA display timings are preferred.
HLEN = InPpl × RiePclk − 1
XPIX = ^{I--n----2P----i-x-} × RiePclk
XINC = ^{O---I--nu---P-t-P--i-x-i--x-} × _{R----4-i-e--0--P-9---c6---l-k-}
XINC needs to be rounded up, it needs to be set to 0 for a
scaling factor of 1.
2004 Mar 04
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