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SAA7104E Datasheet, PDF (49/70 Pages) NXP Semiconductors – Digital video encoder | |||
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Philips Semiconductors
Digital video encoder
Product speciï¬cation
SAA7104E; SAA7105E
7.25 Slave transmitter
Table 112 Slave transmitter (slave address 89H)
REGISTER
FUNCTION
Status byte
Chip ID
FIFO status
SUBADDRESS
00H
1CH
80H
D7
VER2
CID7
0
D6
VER1
CID6
0
D5
VER0
CID5
0
DATA BYTE
D4
D3
CCRDO CCRDE
CID4 CID3
0
0
D2
0
CID2
0
D1
FSEQ
CID1
OVFL
D0
O_E
CID0
UDFL
Table 113 Subaddress 00H
DATA BYTE
VER
CCRDO
CCRDE
FSEQ
O_E
LOGIC
LEVEL
â
1
0
1
0
1
0
1
0
DESCRIPTION
version identiï¬cation of the device: it will be changed with all versions of the IC that have
different programming models; current version is 101 binary
Closed Caption bytes of the odd ï¬eld have been encoded
the bit is reset after information has been written to the subaddresses 67H and 68H; it is
set immediately after the data has been encoded
Closed Caption bytes of the even ï¬eld have been encoded
the bit is reset after information has been written to the subaddresses 69H and 6AH; it is
set immediately after the data has been encoded
during ï¬rst ï¬eld of a sequence (repetition rate: NTSC = 4 ï¬elds, PAL = 8 ï¬elds)
not ï¬rst ï¬eld of a sequence
during even ï¬eld
during odd ï¬eld
Table 114 Subaddress 1CH
DATA BYTE
DESCRIPTION
CID
chip ID of SAA7104E = 04H; chip ID of SAA7105E = 05H
Table 115 Subaddress 80H
DATA BYTE
IFERR
BFERR
OVFL
UDFL
LOGIC
LEVEL
DESCRIPTION
0 normal FIFO state
1 input FIFO overï¬ow/underï¬ow has occurred
0 normal FIFO state
1 buffer FIFO overï¬ow, only if YUPSC = 1
0 no FIFO overï¬ow
1 FIFO overï¬ow has occurred; this bit is reset after this subaddress has been read
0 no FIFO underï¬ow
1 FIFO underï¬ow has occurred; this bit is reset after this subaddress has been read
2004 Mar 04
49
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