SAA7104E Datasheet, PDF (31/70 Pages) NXP Semiconductors – Digital video encoder

Philips Semiconductors
Digital video encoder
Product specification
SAA7104E; SAA7105E
Table 31 Subaddress 29H
DATA BYTE
SRES
BE
LOGIC
LEVEL
DESCRIPTION
0 pin TTX_SRES accepts a teletext bit
stream (TTX)
1 pin TTX_SRES accepts a sync reset input
(SRES)
− ending point of burst in clock cycles
REMARKS
default after reset
a HIGH impulse resets synchronization of the
encoder (first field, first line)
PAL: BE = 29 (1DH); default after reset if
strapping pin FSVGC tied to HIGH
NTSC: BE = 29 (1DH); default after reset if
strapping pin FSVGC tied to LOW
Table 32 Subaddresses 2AH to 2CH
DATA BYTE
CG
CGEN
LOGIC
LEVEL
DESCRIPTION
− LSBs of the respective bytes are encoded immediately after run-in, the MSBs of the
respective bytes have to carry the CRCC bits, in accordance with the definition of copy
generation management system encoding format.
0 copy generation data output is disabled; default after reset
1 copy generation data output is enabled
Table 33 Subaddress 2DH
DATA BYTE
VBSEN
CVBSEN1
CVBSEN0
CEN
ENCOFF
CLK2EN
CVBSEN2
LOGIC
LEVEL
DESCRIPTION
0 pin GREEN_VBS_CVBS provides a component GREEN signal (CVBSEN1 = 0) or CVBS
signal (CVBSEN1 = 1)
1 pin GREEN_VBS_CVBS provides a luminance (VBS) signal; default after reset
0 pin GREEN_VBS_CVBS provides a component GREEN (G) or luminance (VBS) signal;
default after reset
1 pin GREEN_VBS_CVBS provides a CVBS signal
0 pin BLUE_CB_CVBS provides a component BLUE (B) or colour difference BLUE (C_B) signal
1 pin BLUE_CB_CVBS provides a CVBS signal; default after reset
0 pin RED_CR_C_CVBS provides a component RED (R) or colour difference RED (C_R) signal
1 pin RED_CR_C_CVBS provides a chrominance signal (C) as modulated subcarrier for
S-video; default after reset
0 encoder is active; default after reset
1 encoder bypass, DACs are provided with RGB signal after cursor insertion block
0 pin TTXRQ_XCLKO2 provides a teletext request signal (TTXRQ)
1 pin TTXRQ_XCLKO2 provides the buffered crystal clock divided by two (13.5 MHz); default
after reset
0 pin RED_CR_C_CVBS provides a signal according to CEN; default after reset
1 pin RED_CR_C_CVBS provides a CVBS signal
2004 Mar 04
31