SAA7104E Datasheet, PDF (10/70 Pages) NXP Semiconductors – Digital video encoder

Philips Semiconductors
Digital video encoder
Product specification
SAA7104E; SAA7105E
The 8-bit multiplexed C_B-Y-C_R formats are “ITU-R BT.656”
(D1 format) compatible, but the SAV and EAV codes can
be decoded optionally, when the device is operated in
slave mode. For assignment of the input data to the rising
or falling clock edge see Tables 9 to 14.
In order to display interlaced RGB signals through a
euro-connector TV set, a separate digital composite sync
signal (pin HSM_CSYNC) can be generated; it can be
advanced up to 31 periods of the 27 MHz crystal clock in
order to be adapted to the RGB processing of a TV set.
The SAA7104E; SAA7105E synthesizes all necessary
internal signals, colour subcarrier frequency and
synchronization signals from that clock.
Wide screen signalling data can be loaded via the I²C-bus
and is inserted into line 23 for standards using a 50 Hz
field rate.
VPS data for program dependent automatic start and stop
of such featured VCRs is loadable via the I²C-bus.
The IC also contains Closed Caption and extended data
services encoding (line 21), and supports teletext insertion
for the appropriate bit stream format at a 27 MHz clock rate
(see Fig.14). It is also possible to load data for the copy
generation management system into line 20 of every field
(525/60 line counting).
A number of possibilities are provided for setting different
video parameters such as:
• Black and blanking level control
• Colour subcarrier frequency
• Variable burst amplitude etc.
7.1 Reset conditions
To activate the reset a pulse at least of 2 crystal clocks
duration is required.
During reset (RESET = LOW) plus an extra 32 crystal
clock periods, FSVGC, VSVGC, CBO, HSVGC and
TTX_SRES are set to input mode and HSM_CSYNC and
VSM are set to 3-state. A reset also forces the I²C-bus
interface to abort any running bus transfer and sets it into
receive condition.
After reset, the state of the I/Os and other functions is
defined by the strapping pins until an I²C-bus access
redefines the corresponding registers; see Table 2.
Table 2 Strapping pins
PIN
TIED
PRESET
FSVGC
LOW NTSC M encoding, PIXCLK
fits to 640 × 480 graphics
input
HIGH PAL B/G encoding, PIXCLK
fits to 640 × 480 graphics
input
VSVGC
LOW 4 : 2 : 2 Y-C_B-C_R graphics
input (format 0)
HIGH 4 : 4 : 4 RGB graphics input
(format 3)
CBO
LOW input demultiplex phase:
LSB = LOW
HIGH input demultiplex phase:
LSB = HIGH
HSVGC
LOW input demultiplex phase:
MSB = LOW
HIGH input demultiplex phase:
MSB = HIGH
TTXRQ_XCLKO2 LOW slave (FSVGC, VSVGC and
HSVGC are inputs, internal
colour bar is active)
HIGH master (FSVGC, VSVGC
and HSVGC are outputs)
7.2 Input formatter
The input formatter converts all accepted PD input data
formats, either RGB or Y-C_B-C_R, to a common internal
RGB or Y-C_B-C_R data stream.
When double-edge clocking is used, the data is internally
split into portions PPD1 and PPD2. The clock edge
assignment must be set according to the I²C-bus control
bits SLOT and EDGE for correct operation.
If Y-C_B-C_R is being applied as a 27 Mbyte/s data stream,
the output of the input formatter can be used directly to
feed the video encoder block.
The horizontal upscaling is supported via the input
formatter. According to the programming of the pixel clock
dividers (see Section 7.10), it will sample up the data
stream to 1 ×, 2 × or 4 × the input data rate. An optional
interpolation filter is available. The clock domain transition
is handled by a 4 entries wide FIFO which gets initialized
every field or explicitly at request. A bypass for the FIFO is
available, especially for high input data rates.
2004 Mar 04
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