SAA7104E Datasheet, PDF (41/70 Pages) NXP Semiconductors – Digital video encoder

Philips Semiconductors
Digital video encoder
Product specification
SAA7104E; SAA7105E
Table 69 Subaddress 84H
DATA BYTE
DCLK
PCLSY
IFRA
IFBP
PCLE
PCLI
LOGIC
LEVEL
−
0
1
0
1
0
1
−
−
DESCRIPTION
set to logic 1 (default after reset is logic 0)
pixel clock generator runs free; default after reset
pixel clock generator gets synchronized with the vertical sync
input FIFO gets reset explicitly at falling edge
input FIFO gets reset every field; default after reset
input FIFO is active
input FIFO is bypassed; default after reset
controls the divider for the external pixel clock; see Table 70
controls the divider for the internal pixel clock; see Table 71
Table 70 Logic levels and function of PCLE
DATA BYTE
PCLE1
PCLE0
0
0
0
1
1
0
1
1
DESCRIPTION
divider ratio for PIXCLK output is 1
divider ratio for PIXCLK output is 2; default after reset
divider ratio for PIXCLK output is 4
divider ratio for PIXCLK output is 8
Table 71 Logic levels and function of PCLI
DATA BYTE
PCLI1
0
0
1
1
PCLI0
0
1
0
1
DESCRIPTION
divider ratio for internal PIXCLK is 1
divider ratio for internal PIXCLK is 2; default after reset
divider ratio for internal PIXCLK is 4
not allowed
Table 72 Subaddress 85H
DATA BYTE
EIDIV
FILI
LOGIC
LEVEL
0
1
−
DESCRIPTION
set to logic 0 if DVO compliant signals are applied; default after reset
set to logic 1 if non-DVO compliant signals are applied
threshold for FIFO internal transfers; nominal value is 8; default after reset
Table 73 Subaddresses 90H and 94H
DATA BYTE
DESCRIPTION
XOFS
horizontal offset; defines the number of PIXCLKs from horizontal sync (HSVGC) output to composite
blanking (CBO) output
2004 Mar 04
41