306666-11 Datasheet, PDF (68/99 Pages) Numonyx B.V – Numonyx StrataFlash Embedded Memory

P30
13.3.2 Programming the Protection Registers
To program any of the Protection Registers, first issue the Program Protection Register
command at the parameter’s base address plus the offset to the desired Protection
Register (see Section 9.2, “Device Commands” on page 45). Next, write the desired
Protection Register data to the same Protection Register address (see Figure 31,
“Protection Register Map” on page 67).
The device programs the 64-bit and 128-bit user-programmable Protection Register
data 16 bits at a time (see Figure 45, “Protection Register Programming Flowchart” on
page 86). Issuing the Program Protection Register command outside of the Protection
Register’s address space causes a program error (SR[4] set). Attempting to program a
locked Protection Register causes a program error (SR[4] set) and a lock error (SR[1]
set).
Note: When programming the OTP bits for a Top Parameter Device, the following upper address
bits must also be driven properly: A[Max:17] driven high (V_IH) for TSOP and Easy BGA
packages, and A[Max:16] driven high (V_IH) for QUAD+ SCSP.
13.3.3 Locking the Protection Registers
Caution:
Each Protection Register can be locked by programming its respective lock bit in the
Lock Register. To lock a Protection Register, program the corresponding bit in the Lock
Register by issuing the Program Lock Register command, followed by the desired Lock
Register data (see Section 9.2, “Device Commands” on page 45). The physical
addresses of the Lock Registers are 0x80 for register 0 and 0x89 for register 1. These
addresses are used when programming the lock registers (see Table 33, “Device
Identifier Information” on page 70).
Bit 0 of Lock Register 0 is already programmed at the factory, locking the lower, pre-
programmed 64-bit region of the first 128-bit Protection Register containing the unique
identification number of the device. Bit 1 of Lock Register 0 can be programmed by the
user to lock the user-programmable, 64-bit region of the first 128-bit Protection
Register. When programming Bit 1 of Lock Register 0, all other bits need to be left as ‘1’
such that the data programmed is 0xFFFD.
Lock Register 1 controls the locking of the upper sixteen 128-bit Protection Registers.
Each of the 16 bits of Lock Register 1 correspond to each of the upper sixteen 128-bit
Protection Registers. Programming a bit in Lock Register 1 locks the corresponding
128-bit Protection Register.
After being locked, the Protection Registers cannot be unlocked.
Datasheet
68
November 2007
Order Number: 306666-11