306666-11 Datasheet, PDF (19/99 Pages) Numonyx B.V – Numonyx StrataFlash Embedded Memory

P30
4.2
Signal Descriptions
This section has signal descriptions for the various P30 packages.
Table 5: TSOP and Easy BGA Signal Descriptions (Sheet 1 of 2)
Symbol
A[MAX:1]
DQ[15:0]
ADV#
CE#
CLK
OE#
RST#
WAIT
WE#
WP#
VPP
VCC
VCCQ
VSS
Type
Name and Function
Input
Input/
Output
ADDRESS INPUTS: Device address inputs. 64-Mbit: A[22:1]; 128-Mbit: A[23:1]; 256-Mbit:
A[24:1]; 512-Mbit: A[25:1]. Note: The virtual selection of the 256-Mbit “Top parameter” die in the
dual-die 512-Mbit configuration is accomplished by setting A[25] high (V_IH).
DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during
memory, Status Register, Protection Register, and Read Configuration Register reads. Data balls float
when the CE# or OE# are deasserted. Data is internally latched during writes.
Input
ADDRESS VALID: Active low input. During synchronous read operations, addresses are latched on
the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.
In asynchronous mode, the address is latched when ADV# going high or continuously flows through
if ADV# is held low.
WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through.
Input
FLASH CHIP ENABLE: Active low input. CE# low selects the associated flash memory die. When
asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When
deasserted, the associated flash die is deselected, power is reduced to standby levels, data and
WAIT outputs are placed in high-Z state.
WARNING: Chip enable must be driven high when device is not in use.
Input
CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode. During
synchronous read operations, addresses are latched on the rising edge of ADV#, or on the next valid
CLK edge with ADV# low, whichever occurs first.
WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS.
OUTPUT ENABLE: Active low input. OE# low enables the device’s output data buffers during read
Input _{cycles. OE# high places the data outputs and WAIT in High-Z.}
Input
RESET: Active low input. RST# resets internal automation and inhibits write operations. This
provides data protection during power transitions. RST# high enables normal operation. Exit from
reset places the device in asynchronous read array mode.
Output
WAIT: Indicates data valid in synchronous array or non-array burst reads. Read Configuration
Register bit 10 (RCR[10], WT) determines its polarity when asserted. WAIT’s active output is V_OL or
V_OH when CE# and OE# are V_IL. WAIT is high-Z if CE# or OE# is V_IH.
• In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and
valid data when deasserted.
• In asynchronous page mode, and all write modes, WAIT is deasserted.
WRITE ENABLE: Active low input. WE# controls writes to the device. Address and data are latched
Input
on the rising edge of WE#.
Input
WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lock-
down cannot be unlocked with the Unlock command. WP# high overrides the lock-down function
enabling blocks to be erased or programmed using software commands.
Power/
Input
Erase and Program Power: A valid voltage on this pin allows erasing or programming. Memory
contents cannot be altered when V_PP ≤ V_PPLK. Block erase and program at invalid V_PP voltages should
not be attempted.
Set V_PP = V_PPL for in-system program and erase operations. To accommodate resistor or diode drops
from the system supply, the V_IH level of V_PP can be as low as V_PPL min. V_PP must remain above V_PPL
min to perform in-system flash modification. VPP may be 0 V during read operations.
V_PPH can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500
cycles. VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of
this pin at 9 V may reduce block cycling capability.
Power
Power
Device Core Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited
when V_CC ≤ V_LKO. Operations at invalid V_CC voltages should not be attempted.
Output Power Supply: Output-driver source voltage.
Power Ground: Connect to system ground. Do not float any VSS connection.
November 2007
Order Number: 306666-11
Datasheet
19