306666-11 Datasheet, PDF (29/99 Pages) Numonyx B.V – Numonyx StrataFlash Embedded Memory

P30
7.2
Capacitance
Table 15: Capacitance
Parameter
Signals
Min Typ Max
Unit
Condition
Notes
Address, Data,
CE#, WE#, OE#,
Input Capacitance
RST#, CLK, ADV#,
2
6
7
pF
WP#
Output Capacitance
Data, WAIT
2
4
5
pF
Typ temp = 25 °C,
Max temp = 85 °C,
V_CC = (0 V - 2.0 V),
V_CCQ = (0 V - 3.6 V),
Discrete silicon die
1,2,3
Notes:
1.
Capacitance values are for a single die; for 2-die and 4-die stacks, multiply the capacitance values by the number of
dies in the stack.
2.
Sampled, but not 100% tested.
3.
Silicon die capacitance only; add 1 pF for discrete packages.
7.3
AC Read Specifications
Table 16: AC Read Specifications for 64/128- Mbit Densities (Sheet 1 of 2)
Num
Symbol
Parameter
Min
Max
Unit
Asynchronous Specifications
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
t_AVAV
t_AVQV
t_ELQV
t_GLQV
t_PHQV
t_ELQX
t_GLQX
t_EHQZ
t_GHQZ
t_OH
Read cycle time
Address to output valid
CE# low to output valid
OE# low to output valid
RST# high to output valid
CE# low to output in low-Z
OE# low to output in low-Z
CE# high to output in high-Z
OE# high to output in high-Z
Output hold from first occurring address, CE#, or
OE# change
R11
R12
R13
R15
R16
R17
t_EHEL
t_ELTV
t_EHTZ
t_GLTV
t_GLTX
t_GHTZ
CE# pulse width high
CE# low to WAIT valid
CE# high to WAIT high-Z
OE# low to WAIT valid
OE# low to WAIT in low-Z
OE# high to WAIT in high-Z
Latching Specifications
R101
R102
R103
R104
R105
R106
t_AVVH
t_ELVH
t_VLQV
t_VLVH
t_VHVL
t_VHAX
Address setup to ADV# high
CE# low to ADV# high
ADV# low to output valid
ADV# pulse width low
ADV# pulse width high
Address hold from ADV# high
85
-
ns
-
85
ns
-
85
ns
-
25
ns
-
150
ns
0
-
ns
0
-
ns
-
24
ns
-
24
ns
0
-
ns
20
-
ns
-
17
ns
-
20
ns
-
17
ns
0
-
ns
-
20
ns
10
-
ns
10
-
ns
-
85
ns
10
-
ns
10
-
ns
9
-
ns
Notes
1,2
1
1,3
1,2,3
1,3
1
1,3
1
1,3
1
1,4
November 2007
Order Number: 306666-11
Datasheet
29