306666-11 Datasheet, PDF (34/99 Pages) Numonyx B.V – Numonyx StrataFlash Embedded Memory

P30
Figure 16: Asynchronous Page-Mode Read Timing
R1
R2
A[Max:2] [A]
A[1:0]
ADV#
R101
R105
R106
R3
CE# [E]
R4
OE# [G]
R15
WAIT [T]
R7
DATA [D/Q]
R108
Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low).
R8
R10
R17
R9
Figure 17: Synchronous Single-Word Array or Non-array Read Timing
CLK [C]
R301
R306
Address [A]
ADV# [V]
CE# [E]
OE# [G]
WAIT [T]
R105
R101
R104
R303
R102
R106
R7
R15
Data [D/Q]
R2
R3
R4
R307
R304
R8
R9
R312 R17
R305
1.
WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either
during or one data cycle before valid data.
2.
This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by
CE# deassertion after the first word in the burst.
Datasheet
34
November 2007
Order Number: 306666-11