306666-11 Datasheet, PDF (30/99 Pages) Numonyx B.V – Numonyx StrataFlash Embedded Memory

P30
Table 16: AC Read Specifications for 64/128- Mbit Densities (Sheet 2 of 2)
Num
Symbol
Parameter
Min
Max
Unit Notes
R108
R111
t_APA
t_phvh
Clock Specifications
Page address access
RST# high to ADV# high
-
25
ns
1
30
-
ns
R200
f_CLK
CLK frequency
R201
t_CLK
CLK period
R202
t_CH/CL
CLK high/low time
R203
t_FCLK/RCLK
CLK fall/rise time
Synchronous Specifications^(5,6)
-
52
MHz
TSOP
-
40
MHz
19.2
-
TSOP
25
-
ns
1,3,5,6
ns
5
-
ns
-
3
ns
R301
t_AVCH/L
Address setup to CLK
9
-
ns
R302
R303
t_VLCH/L
t_ELCH/L
ADV# low setup to CLK
CE# low setup to CLK
9
-
ns
1
9
-
ns
R304
t_{CHQV / tCLQV}
CLK to output valid
-
17
ns
R305
t_CHQX
Output hold from CLK
3
-
ns
1,7
R306
t_CHAX
Address hold from CLK
10
-
ns
1,4,7
R307
t_CHTV
CLK to WAIT valid
-
17
ns
1,7
R311
t_CHVL
CLK Valid to ADV# Setup
3
-
ns
1
R312
t_CHTX
WAIT Hold from CLK
3
-
ns
1,7
Notes:
1.
See Figure 11, “AC Input/Output Reference Waveform” on page 28 for timing measurements and max
allowable input slew rate.
2.
OE# may be delayed by up to t_ELQV – t_GLQV after CE#’s falling edge without impact to t_ELQV.
3.
Sampled, not 100% tested.
4.
Address hold in synchronous burst mode is t_CHAX or t_VHAX, whichever timing specification is satisfied first.
5.
Please see the latest P30 Spec Update for synchronous burst operation with the TSOP package.
6.
Synchronous read mode is not supported with TTL level inputs.
7.
Applies only to subsequent synchronous reads.
Table 17: AC Read Specifications for 256/512-Mbit Densities (Sheet 1 of 3)
Num
Symbol
Parameter
Speed
Min
Max
Unit
Asynchronous Specifications
R1
t_AVAV
Read cycle time
R2
t_AVQV
Address to output valid
V_CC = 1.8 V – 2.0
V
85
-
V_CC = 1.7 V – 2.0
V
88
-
ns
256/512-Mb TSOP
packages
95
V_CC = 1.8 V – 2.0
V
-
85
V_CC = 1.7 V – 2.0
V
-
88
ns
256/512-Mb TSOP
packages
-
95
Notes
Datasheet
30
November 2007
Order Number: 306666-11