306666-11 Datasheet, PDF (35/99 Pages) Numonyx B.V – Numonyx StrataFlash Embedded Memory

P30
Figure 18: Continuous Burst Read, Showing An Output Delay Timing
CLK [C]
Address [A]
ADV# [V]
CE# [E]
R301
R302
R306
R2
R101
R105
R106
R303
R102
R3
R304
R304
R304
OE# [G]
R15
R307
R312
WAIT [T]
Data [D/Q]
R4
R7
R304
R305
R305
R305
R305
Notes:
1.
WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either
during or one data cycle before valid data.
2.
At the end of Word Line; the delay incurred when a burst access crosses a 16-word boundary and the starting address is
not 4-word boundary aligned.
Figure 19: Synchronous Burst-Mode Four-Word Read Timing
y
CLK [C]
R302
R301 R306
R2
R101
Address [A]
A
ADV# [V]
R105
R106
R102
R303
CE# [E]
OE# [G]
WAIT [T]
Data [D/Q]
R3
R15
R4
R7
R307
R304
R304
R305
Q0
Q1
R8
R9
R17
R10
Q2
Q3
Note: WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during initial latency and
deasserted during valid data (RCR[10] = 0, Wait asserted low).
November 2007
Order Number: 306666-11
Datasheet
35