306666-11 Datasheet, PDF (36/99 Pages) Numonyx B.V – Numonyx StrataFlash Embedded Memory

P30
7.4
AC Write Specifications
Table 19: AC Write Specifications
Num Symbol
Parameter
Min
Max
Unit
Notes
W1
t_PHWL
RST# high recovery to WE# low
W2
t_ELWL
CE# setup to WE# low
W3
t_WLWH
WE# write pulse width low
W4
t_DVWH
Data setup to WE# high
W5
t_AVWH
Address setup to WE# high
W6
t_WHEH
CE# hold from WE# high
W7
t_WHDX
Data hold from WE# high
W8
t_WHAX
Address hold from WE# high
W9
t_WHWL
WE# pulse width high
W10
t_VPWH
V_PP setup to WE# high
W11
t_QVVL
V_PP hold from Status read
W12
t_QVBL
WP# hold from Status read
W13
t_BHWH
WP# setup to WE# high
W14
t_WHGL
WE# high to OE# low
W16
t_WHQV
WE# high to read valid
Write to Asynchronous Read Specifications
150
-
0
-
50
-
50
-
50
-
0
-
0
-
0
-
20
-
200
-
0
-
0
-
200
-
0
-
t_AVQV + 35
-
ns
1,2,3
ns
1,2,3
ns
1,2,4
ns
ns
ns
1,2
ns
ns
ns
1,2,5
ns
1,2,3,7
ns
ns
1,2,3,7
ns
ns
1,2,9
ns
1,2,3,6,10
W18
t_WHAV
WE# high to Address valid
Write to Synchronous Read Specifications
0
-
ns
1,2,3,6,8
W19
t_WHCH/L
WE# high to Clock valid
W20
t_WHVH
WE# high to ADV# high
Write Specifications with Clock Active
19
-
ns
1,2,3,6,10
19
-
ns
W21
W22
t_VHWL
t_CHWL
ADV# high to WE# low
Clock high to WE# low
-
20
ns
1,2,3,11
-
20
ns
Notes:
1.
Write timing characteristics during erase suspend are the same as write-only operations.
2.
A write operation can be terminated with either CE# or WE#.
3.
Sampled, not 100% tested.
4.
Write pulse width low (t_WLWH or t_ELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high
(whichever occurs first). Hence, t_WLWH = t_ELEH = t_WLEH = t_ELWH.
5.
Write pulse width high (t_WHWL or t_EHEL) is defined from CE# or WE# high (whichever occurs first) to CE# or WE# low
(whichever occurs last). Hence, t_WHWL = t_EHEL = t_WHEL = t_EHWL).
6.
t_WHVH or t_WHCH/L must be met when transitioning from a write cycle to a synchronous burst read.
7.
V_PP and WP# should be at a valid level until erase or program success is determined.
8.
This specification is only applicable when transitioning from a write cycle to an asynchronous read. See spec W19 and
W20 for synchronous read.
9.
When doing a Read Status operation following any command that alters the Status Register, W14 is 20 ns.
10.
Add 10 ns if the write operation results in a RCR or block lock status change, for the subsequent read operation to reflect
this change.
11.
These specs are required only when the device is in a synchronous mode and clock is active during address setup phase.
Datasheet
36
November 2007
Order Number: 306666-11