306666-11 Datasheet, PDF (43/99 Pages) Numonyx B.V – Numonyx StrataFlash Embedded Memory

P30
9.0
Device Operations
This section provides an overview of device operations. The system CPU provides
control of all in-system read, write, and erase operations of the device via the system
bus. The on-chip Write State Machine (WSM) manages all block-erase and word-
program algorithms.
Device commands are written to the Command User Interface (CUI) to control all flash
memory device operations. The CUI does not occupy an addressable memory location;
it is the mechanism through which the flash device is controlled.
9.1
Bus Operations
CE# low and RST# high enable device read operations. The device internally decodes
upper address inputs to determine the accessed block. ADV# low opens the internal
address latches. OE# low activates the outputs and gates selected data onto the I/O
bus.
In asynchronous mode, the address is latched when ADV# goes high or continuously
flows through if ADV# is held low. In synchronous mode, the address is latched by the
first of either the rising ADV# edge or the next valid CLK edge with ADV# low (WE#
and RST# must be V_IH; CE# must be V_IL).
Bus cycles to/from the P30 device conform to standard microprocessor bus operations.
Table 22 summarizes the bus operations and the logic levels that must be applied to
the device control signal inputs.
Table 22: Bus Operations Summary
Bus Operation
RST#
CLK
ADV#
CE#
OE#
WE#
WAIT
DQ[15:0
]
Notes
Asynchronous
V_IH
X
L
L
L
H
Deasserted
Output
Read
Synchronous
V_IH
Running
L
L
L
H
Driven
Output
Write
V_IH
X
L
L
H
L
High-Z
Input
1
Output Disable
V_IH
X
X
L
H
H
High-Z
High-Z
2
Standby
V_IH
X
X
H
X
X
High-Z
High-Z
2
Reset
V_IL
X
X
X
X
X
High-Z
High-Z
2,3
Notes:
1.
Refer to the Table 23, “Command Bus Cycles” on page 45 for valid DQ[15:0] during a write
operation.
2.
X = Don’t Care (H or L).
3.
RST# must be at V_SS ± 0.2 V to meet the maximum specified power-down current.
9.1.1
Reads
To perform a read operation, RST# and WE# must be deasserted while CE# and OE#
are asserted. CE# is the device-select control. When asserted, it enables the flash
memory device. OE# is the data-output control. When asserted, the addressed flash
memory data is driven onto the I/O bus. See Section 10.0, “Read Operations” on
page 48 for details on the available read modes, and see Section 14.0, “Special Read
States” on page 69 for details regarding the available read states.
November 2007
Order Number: 306666-11
Datasheet
43