CP3BT26 Datasheet, PDF (93/278 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth-R, USB, and CAN Interfaces

Receive Endpoint FIFO Operation (RXFIFO1, RXFIFO2,
RXFIFO3)
The Receive FIFOs for endpoints 2, 4, and 6 support bulk,
interrupt, and isochronous USB packet transfers larger than
the actual FIFO size. If the packet length exceeds the FIFO
size, software must read the FIFO contents while the USB
packet is being received on the bus. Figure 32 shows the
detailed behavior of receive FIFOs.
18.3 USB CONTROLLER REGISTERS
The CR16 USB node has a set of memory-mapped regis-
ters that can be read/written from the CPU bus to control the
USB interface. Some register bits are reserved; reading
from these bits returns undefined data. Reserved register
bits must always be written with 0.
Table 40 USB Controller Registers
FLUSH (Resets RXRP and RXWP)
Name
MCNTRL
Address
FF FD80h
Description
Main Control Register
RFnS - 1
0X0
RXRP
NFSR
FF FD8Ah
Node Functional State
Register
+
RCOUNT = RXWP - RXRF
+
MAEV
ALTEV
FF FD8Ch
FF FD90h
Main Event Register
Alternate Event
Register
RX FIFO n
RXWP
MAMSK
FF FD8Eh Main Mask Register
+
ALTMSK
FF FD92h
Alternate Mask
Register
TXEV
FF FD94h
Transmit Event
Register
RXFL = RXRP - RXWP (= RFnS - RCOUNT)
DS052
TXMSK
FF FD96h
Transmit Mask
Register
Figure 32. Receive FIFO Operation
RFnS
RXRP
RXWP
RXFL
RCOUNT
The Receive FIFO n Size is the total number
of bytes available within the FIFO.
The Receive Read Pointer is incremented
with every read by software from the receive
FIFO. This pointer wraps around to zero if
RFnS is reached. RXRP is never incremented
beyond the value of RXWP. If an attempt is
made to read more bytes than are actually
available (FIFO underrun), the last byte is
read repeatedly.
The Receive Write Pointer is incremented ev-
ery time the Endpoint Controller writes to the
receive FIFO. This pointer wraps around to
zero if RFnS is reached. An overrun condition
occurs if RXRP equals RXWP and an attempt
is made to write an additional byte.
The Receive FIFO Level indicates how many
more bytes can be received until an overrun
condition occurs with the next write to the
FIFO. A FIFO warning is issued if RXFL de-
creases to a specific value. The respective
WARNn bit in the FWR register is set if RXFL
is equal to or less than the number specified
by the RFWL bit in the RXCn register.
The Receive FIFO Count indicates how many
bytes can be read from the receive FIFO. This
value is accessible by software via the RXSn
register.
RXEV
RXMSK
NAKEV
NAKMSK
FWEV
FWMSK
FNH
FNL
FAR
DMACNTRL
DMAEV
DMAMSK
MIR
DMACNT
DMAERR
FF FD98h
FF FD9Ah
FF FD9Ch
FF FD9Eh
FF FDA0h
FF FDA2h
FF FDA4h
FF FDA6h
FF FD88h
FF FDA8h
FF FDAAh
FF FDACh
FF FDAEh
FF FDB0h
FF FDB2h
Receive Event
Register
Receive Mask
Register
NAK Event Register
NAK Mask Register
FIFO Warning Event
Register
FIFO Warning Mask
Register
Frame Number High
Byte Register
Frame Number Low
Byte Register
Function Address
Register
DMA Control Register
DMA Event Register
DMA Mask Register
Mirror Register
DMA Count Register
DMA Error Register
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