CP3BT26 Datasheet, PDF (83/278 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth-R, USB, and CAN Interfaces

3. By extension, the ADC negative voltage reference can
be internally connected to the TSY- terminal, to recover
the full 4096 values.
The Global Configuration Register (ADCGCR) provides the
flexibility to implement any of these techniques.
16.3 ADC OPERATION IN POWER-SAVING
MODES
To reduce the level of switching noise in the environment of
the ADC, it is possible to operate the CP3BT26 in low-power
modes, in which the System Clock is slowed or switched off.
Under these conditions, Auxiliary Clock 2 can be selected
as the clock source for the ADC module, however conver-
sion results cannot be read by the system while the System
Clock is suspended. The expected operation in power-sav-
ing modes is therefore:
1. ADC is configured and a conversion is primed or trig-
gered.
2. A power-saving mode is entered.
3. ADC conversion completes and a wake-up signal is as-
serted to the MIWU unit.
4. Device wakes up and processes the conversion result.
16.5 ADC REGISTER SET
Table 34 lists the ADC registers.
Table 34 ADC Registers
Name
ADCGCR
ADCACR
ADCCNTRL
ADCSTART
ADCSCDLY
ADCRESLT
Address
FF F3C0h
FF F3C2h
FF F3C4h
FF F3C6h
FF F3C8h
FF F3CAh
Description
ADC Global
Configuration Register
ADC Auxiliary
Configuration Register
ADC Conversion
Control Register
ADC Start Conversion
Register
ADC Start Conversion
Delay Register
ADC Result Register
To conserve power, the ADC should be disabled before en-
tering a low-power mode if its function is not required.
16.4 FREEZE
The ADC module provides support for an In-System Emula-
tor by means of a special FREEZE input. When FREEZE is
asserted the module will exhibit the following specific be-
havior:
„ The automatic clear-on-read function of the result regis-
ter (ADCRESLT) is disabled.
„ The FIFO is updated as usual, and an interrupt for a
completed conversion can be asserted.
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