CP3BT26 Datasheet, PDF (70/278 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth-R, USB, and CAN Interfaces

14.1.6 Port High Drive Strength Register (PxHDRV)
The PxHDRV register is a byte-wide, read/write register that
controls the slew rate of the corresponding pins. The high
drive strength function is enabled when the corresponding
bits of the PxHDRV register are set. In both GPIO and alter-
nate function modes, the drive strength function is enabled
by the PxHDRV registers. At reset, the PxHDRV registers
are cleared, making the ports low speed.
7
0
PxHDRV
PxHDRV
The PxHDRV bits control whether output pins
are driven with slow or fast slew rate.
0 – Slow slew rate.
1 – Fast slew rate.
14.1.7 Port Alternate Function Select Register
(PxALTS)
The PxALTS register selects which of two alternate func-
tions are selected for the port pin. These bits are ignored
unless the corresponding PxALT bits are set. Each port pin
can be controlled independently.
7
0
PxALTS
PxALTS
The PxALTS bits select among two alternate
functions. Table 30 shows the mapping of the
PxALTS bits to the alternate functions. Un-
used PxALTS bits must be clear.
Table 30 Alternate Function Select
Port Pin
PE0
PE1
PE2
PE3
PE4
PE5
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PxALTS = 0
UART0 RXD0
UART0 TXD0
UART0 RTS
UART0 CTS
UART0 CKX
SRFS
MSK
MDIDO
MDODI
MWCS
SCK
SFS
STD
PxALTS = 1
Reserved
Reserved
Reserved
Reserved
TB
NMI
TIO1
TIO2
TIO3
TIO4
TIO5
TIO6
TIO7
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Table 30 Alternate Function Select
Port Pin
PF7
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
PJ0
PJ1
PJ2
PJ3
PJ4
PJ5
PJ6
PJ7
PxALTS = 0
SRD
RFSYNC
RFCE
BTSEQ1
SCLK
SDAT
SLE
WUI10
TA
UART1 RXD1
UART1 TXD1
UART2 RXD2
UART2 TXD2
UART3 RXD3
UART3 TXD3
CANRX
CANTX
WUI18
WUI19
WUI20
WUI21
WUI22
WUI23
WUI24
ASYNC
PxALTS = 1
TIO8
Reserved
Reserved
SRCLK
Reserved
Reserved
Reserved
BTSEQ2
BTSEQ3
WUI11
WUI12
WUI13
WUI14
WUI15
WUI16
WUI17
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
WUI9