CP3BT26 Datasheet, PDF (118/278 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth-R, USB, and CAN Interfaces

Bus
Signal
CAN
Clock
PREVIOUS
BIT
A
e
TSEG1
"NORMAL" BIT TIME
TSEG2
NEXT BIT
PREVIOUS
BIT
A
TSEG1
SJW
BIT TIME LENGTHENED BY SJW
TSEG2
Figure 45. Resynchronization (e > SJW)
NEXT BIT
DS029
Bus
Signal
CAN
Clock
PREVIOUS
BIT
A
e
TSEG1
"NORMAL" BIT TIME
TSEG2
PREVIOUS
BIT
A
TSEG1
TSEG2
BIT TIME SHORTENED BY SJW
NEXT BIT
DS030
Figure 46. Resynchronization (e < -SJW)
19.2.7 Clock Generator
The CAN prescaler (PSC) is shown is Figure 47. It divides
the CKI input clock by the value defined in the CTIM register.
The resulting clock is called time quanta clock and defines
the length of one time quantum (tq).
Please refer to CAN Timing Register (CTIM) on page 135
for a detailed description of the CTIM register.
Note: PSC is the value of the clock prescaler. TSEG1 and
TSEG2 are the length of time segment 1 and 2 in time quan-
ta.
PSC = PSC[5:0] + 2
TSEG1 = TSEG1[3:0] + 1
TSEG2 = TSEG2[2:0] + 1
CKI
÷ PSC
÷ (1+TSEG1+TSEG2)
Internal Time
Quanta Clock (1/tq)
Figure 47. CAN Prescaler
Bit Rate
DS031
The resulting bus clock can be calculated by the equation: 19.3 MESSAGE TRANSFER
busclock = --------------------------------------C----K-----I-------------------------------------
(PSC)x(1 + TSEG1 + TSEG2)
The values of PSC, TSEG1, and TSEG2 are specified by
the contents of the registers PSC, TSEG1, and TSEG2 as
follows:
The CAN module has access to 15 independent message
buffers, which are memory mapped in RAM. Each message
buffer consists of 8 different 16-bit RAM locations and can
be individually configured as a receive message buffer or as
a transmit message buffer.
A dedicated acceptance filtering procedure enables soft-
ware to configure each buffer to receive only a single mes-
sage ID or a group of messages. One buffer uses an
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