CP3BT26 Datasheet, PDF (263/278 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth-R, USB, and CAN Interfaces

30.16 EXTERNAL BUS TIMING
Table 93 External Bus Signals
Symbol Figure
Description
Reference
External Bus Input Signals
131,
t₁
133, Input Setup Time
134, D[15:0]
135
131,
t₂
133, Output Hold Time
134, D[15:0]
135
Before Rising Edge (RE)
on CLK
After RE on CLK
External Bus Output Signals
t₃
131, Output Valid Time
132 D[15:0]
131,
t₄
132,
133,
134,
Output Valid Time
A[22:0]
135
t₅
131,
132,
133,
134,
135
Output Active/Inactive Time
RD
SEL[1:0]
SELIO
t₆
131, Output Active/Inactive Time
132 WR[1:0]
t₇
133
Minimum Inactive Time
RD
t₈
131
Output Float Time
D[15:0]
t₉
131 Minimum Delay Time
t₁₀
131,
132
Minimum Delay Time
t₁₁ 132 Minimum Delay Time
t₁₂
131,
132,
133,
134,
135
Output Hold Time
A[22:0]
D[15:0]
RD
SEL[2:0]
SELIO
t₁₃
131, Output Hold Time
132 WR[1:0]
After RE on CLK
After RE on CLK
After RE on CLK
After RE on CLK
At 2.0V
After RE on CLK
From RD Trailing Edge
(TE) to D[15:0] driven
From RD TE to SELn
Leading Edge (LE)
From SELx TE to SELy LE
After RE on CLK
After RE on CLK
Min (ns)
8
0
-
-
-
-
Tclk - 4
-
Tclk - 4
0
0
0
0.5 Tclk - 3
Max (ns)
-
-
8
8
8
0.5 Tclk + 8
-
8
-
-
-
-
-
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