CP3BT26 Datasheet, PDF (178/278 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth-R, USB, and CAN Interfaces

23.3 SLAVE MODE
23.4 INTERRUPT GENERATION
In Slave mode, the MSK pin is an input for the shift clock
MSK. MDIDO is placed in TRI-STATE mode when MWCS is
inactive. Data transfer is enabled when MWCS is active.
The slave starts driving MDIDO when MWCS is active. The
most significant bit (lower byte in 8-bit mode or upper byte
in 16-bit mode) is output onto the MDIDO pin first. After
eight or sixteen clocks (depending on the selected mode),
the data transfer is completed.
If a new shift process starts before MWDAT was written, i.e.,
while MWDAT does not contain any valid data, and the
ECHO bit is set, the data received from MDODI is transmit-
ted on MDIDO in addition to being shifted to MWDAT. If the
ECHO bit is clear, the data transmitted on MDIDO is the
data held in the MWDAT register, regardless of its validity.
The master may negate the MWCS signal to synchronize
the bit count between the master and the slave. In the case
that the slave is the only slave in the system, MWCS can be
tied to ground.
Interrupts may be enabled for any of the conditions shown
in Table 73.
Table 73 Microwire Interrupt Trigger Condition
Condition
Status
Bit in the
MWSTAT
Register
Interrupt
Enable Bit
in the
MWCTRL1
Register
Description
Not Busy BSY
Read
Buffer Full
RBF
Overrun OVF
The shifter is ready
EIW for the next data
transfer sequence.
The read buffer is
EIR full and waiting to be
unloaded.
A new data transfer
sequence started
EIO while both the shifter
and the read buffer
were full.
Figure 89 illustrates the interrupt generation logic of this
module.
EIO
OVR = 1
EIR
RBF = 1
EIW
MWSPI
Interrupt
BSY = 0
DS073
Figure 89. MWSPI Interrupts
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