CP3BT26 Datasheet, PDF (9/278 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth-R, USB, and CAN Interfaces

Table 2 CP3BT26 LQFP-128 Signal Descriptions
Name Pins I/O
Primary Function
Alternate
Name
Alternate Function
X1CKI
X1CKO
X2CKI
X2CKO
RESET
ENV0
ENV1
ENV2
TMS
TCK
TDI
TDO
RDY
VCC
GND
IOVCC
IOGND
AVCC
AGND
ADVCC
ADGND
RFDATA
SCL
SDA
D-
D+
UVCC
UGND
ADC0
ADC1
ADC2
1 Input 12 MHz Oscillator Input
1 Output 12 MHz Oscillator Output
1 Input 32 kHz Oscillator Input
1 Output 32 kHz Oscillator Output
1 Input Chip general reset
1 I/O
Special mode select input with
internal pull-up during reset
1 I/O
Special mode select input with
internal pull-up during reset
1 I/O
Special mode select input with
internal pull-up during reset
1 Input
JTAG Test Mode Select
(with internal weak pull-up)
1 Input
JTAG Test Clock Input
(with internal weak pull-up)
1 Input
JTAG Test Data Input
(with internal weak pull-up)
1 Output JTAG Test Data Output
1 Output NEXUS Ready Output
6 Input
2.5V Core Logic
Power Supply
6 Input Core Ground
15 Input 2.5–3.3V I/O Power Supply
14 Input I/O Ground
1 Input PLL Analog Power Supply
1 Input PLL Analog Ground
1 Input ADC Analog Power Supply
1 Input ADC Analog Ground
1 I/O
Bluetooth RX/TX Data Pin
1 I/O
ACCESS.bus Clock
1 I/O
ACCESS.bus Serial Data
1 I/O
USB D- Upstream Port
1 I/O
USB D+ Upstream Port
1 Input 3.3V USB Transceiver Supply
1 Input USB Transceiver Ground
1 I/O
ADC Input Channel 0
1 I/O
ADC Input Channel 1
1 I/O
ADC Input Channel 2
BBCLK
None
None
None
None
PLLCLK
BB reference clock for the RF Interface
None
None
None
None
PLL Clock Output
CPUCLK CPU Clock Output
SLOWCLK Slow Clock Output
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
TSX+
TSY+
TSX-
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Touchscreen X+ contact
Touchscreen Y+ contact
Touchscreen X- contact
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