CP3BT26 Datasheet, PDF (126/278 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth-R, USB, and CAN Interfaces

19.7.1 Highest Priority Interrupt Code
Table 49 Highest Priority Interrupt Code (ICEN=FFFF)
To reduce the decoding time for the CIPND register, the
buffer interrupt request with the highest priority is placed as
interrupt status code into the IST[3:0] section of the CSTP-
ND register.
Each of the buffer interrupts as well as the error interrupt
can be individually enabled or disabled in the CAN Interrupt
Enable register (CIEN). As soon as an interrupt condition
occurs, every interrupt request is indicated by a flag in the
CAN Interrupt Pending register (CIPND). When the interrupt
code logic for the present highest priority interrupt request
is enabled, this interrupt will be translated into the IST3:0
bits of the CAN Status Pending register (CSTPND). An in-
terrupt request can be cleared by setting the corresponding
bit in the CAN Interrupt Clear register (CICLR).
Figure 59 shows the CAN interrupt management.
CAN Interrupt
Request
IRQ
IST3
IST2
IST1
IST0
Buffer 10
Buffer 11
1
1
0
1
1
1
1
1
0
0
Buffer 12
1
1
1
0
1
Buffer 13
Buffer 14
1
1
1
1
0
1
1
1
1
1
19.7.2 Usage Hints
The interrupt code IST3:0 can be used within the interrupt
handler as a displacement to jump to the relevant subrou-
tine.
CIEN
CICLR
CIPND
Clear interrupt flags of every
message buffer individually
The CAN Interrupt Code Enable (CICEN) register is used in
the CAN interrupt handler if software is servicing all receive
buffer interrupts first, followed by all transmit buffer inter-
rupts. In this case, software can first enable only receive
buffer interrupts to be coded, then scan and service all
pending interrupt requests in the order of their priority. After
processing all the receive interrupts, software changes the
CICEN register to disable all receive buffers and enable all
transmit buffers, then services all pending transmit buffer in-
terrupt requests according to their priorities.
CICEN
19.8 TIME STAMP COUNTER
ICODE
IRQ IST3 IST2 IST1 IST0
DS043
Figure 59. Interrupt Management
The highest priority interrupt source is translated into the
bits IRQ and IST3:0 as shown in Table 49.
Table 49 Highest Priority Interrupt Code (ICEN=FFFF)
The CAN module features a free running 16-bit timer (CT-
MR) incrementing every bit time recognized on the CAN
bus. The value of this timer during the ACK slot is captured
into the TSTP register of a message buffer after a success-
ful transmission or reception of a message. Figure 60
shows a simplified block diagram of the Time Stamp
counter.
CAN bits on the bus
ACK slot and buffer 0 active
+ 1 _{16-Bit counter}
Reset
CAN Interrupt
Request
IRQ
IST3
IST2
IST1
IST0
ACK slot
No Request
0
0
0
0
0
Error Interrupt 1
0
0
0
0
TSTP register
DS044
Buffer 0
Buffer 1
Buffer 2
Buffer 3
Buffer 4
Buffer 5
1
0
0
0
1
Figure 60. Time Stamp Counter
1
0
0
1
0
The timer can be synchronized over the CAN network by re-
1
0
0
1
1
ceiving or transmitting a message to or from buffer 0. In this
1
0
1
0
0
case, the TSTP register of buffer 0 captures the current
CTMR value during the ACK slot of a message (as above),
1
0
1
0
1
and then the CTMR is reset to 0000b. Synchronization can
1
0
1
1
0
be enabled or disabled using the CGCR.TSTPEN bit.
Buffer 6
1
0
1
1
1
Buffer 7
1
1
0
0
0
Buffer 8
1
1
0
0
1
Buffer 9
1
1
0
1
0
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