CP3BT26 Datasheet, PDF (258/278 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth-R, USB, and CAN Interfaces

30.12 ACCESS.BUS TIMING
Table 89 ACCESS.bus Signals
Symbol Figure
Description
Reference
ACCESS.bus Input Signals
t_BUFi
t_CSTOsi
t_CSTRhi
t_CSTRsi
t_DHCsi
t_DLCsi
t_SCLfi
t_SCLri
t_SCLlowi
t_SCLhighi
t_SDAri
t_SDAfl
t_SDAhi
t_SDAsi
126
Bus free time between Stop and Start
Condition
126 SCL setup time
Before Stop Condition
126 SCL hold time
After Start Condition
126 SCL setup time
127 Data High setup time
Before Start Condition
Before SCL Rising Edge
(RE)
126 Data Low setup time
Before SCL RE
125 SCL signal rise time
125 SCL signal fall time
128 SCL low time
After SCL Falling Edge
(FE)
128 SCL high time
After SCL RE
125 SDA signal rise time
125 SDA signal fall time
128 SDA hold time
After SCL FE
128 SDA setup time
Before SCL RE
ACCESS.bus Output Signals
t_BUFo
126 _{Bus free time between Stop and Start}
Condition
t_CSTOso 126 SCL setup time
t_CSTRho 126 SCL hold time
t_CSTRso 127 SCL setup time
t_DHCso 127 Data High setup time
t_DLCso 126 Data Low setup time
t_SCLfo
125 SCL signal Fall time
t_SCLro 125 SCL signal Rise time
t_SCLlowo 128 SCL low time
t_SCLhigho 128 SCL high time
t_SDAfo
125 SDA signal Fall time
t_SDAro 125 SDA signal Rise time
t_SDAho 128 SDA hold time
t_SDAvo 128 SDA valid time
Before Stop Condition
After Start Condition
Before Start Condition
Before SCL R.E.
Before SCL R.E.
After SCL F.E.
After SCL R.E.
After SCL F.E.
After SCL F.E.
Min (ns)
Max (ns)
t_SCLhigho
(8 × t_CLK) - t_SCLri
(8 × t_CLK) - t_SCLri
(8 × t_CLK) - t_SCLri
2 × t_CLK
2 × t_CLK
-
-
16 × t_CLK
16 × t_CLK
-
-
0
2 × t_CLK
-
-
-
-
-
-
300
1000
-
-
1000
300
-
-
t_SCLhigho
-
t_SCLhigho
t_SCLhigho
t_SCLhigho
t_SCLhigho -t_SDAro
t_SCLhigho -t_SDAfo
-
-
(K × t_CLK) -1^e
(K × t_CLK) -1^e
-
-
-
-
-
-
300^c
-^d
-
-
300
-
-
(7 × t_CLK) - t_SCLfo
-
(7 × t_CLK) + t_RD
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