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CP3BT26 Datasheet, PDF (166/278 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth-R, USB, and CAN Interfaces
parity bit is generated and transmitted following the eight
data bits.
Table 69 Prescaler Factors (Continued)
Prescaler Select
Prescaler Factor
Start
2
Bit
Start
2a
Bit
Start
2b
Bit
8-Bit Data
8-Bit Data
8-Bit Data
1S
2S
PA 1S
01011
6
01100
6.5
01101
7
01110
7.5
01111
8
10000
8.5
Start
2c
Bit
8-Bit Data
PA
2S
10001
9
DS064
10010
9.5
10011
10
Figure 80. 8-Bit Data Frame Options
10100
10.5
The format shown in Figure 81 consists of one start bit, nine
data bits, and one or two stop bits. This format also supports
10101
11
the UART attention feature. When operating in this format,
10110
11.5
all eight bits of UnTBUF and UnRBUF are used for data.
The ninth data bit is transmitted and received using two bits
10111
12
in the control registers, called UXB9 and URB9. Parity is not
11000
12.5
generated or verified in this mode.
11001
13
Start
3
Bit
9-Bit Data
1S
11010
13.5
11011
14
Start
3a
Bit
9-Bit Data
2S
11100
11101
14.5
15
DS065
11110
15.5
Figure 81. 9-bit Data Frame Options
22.2.6 Baud Rate Generator
The Baud Rate Generator creates the basic baud clock from
the System Clock. The System Clock is passed through a
two-stage divider chain consisting of a 5-bit baud rate pres-
caler (UnPSC) and an 11-bit baud rate divisor (UnDIV).
The relationship between the 5-bit prescaler select (UnP-
SC) setting and the prescaler factors is shown in Table 69.
Table 69 Prescaler Factors
Prescaler Select
00000
00001
Prescaler Factor
No clock
1
11111
16
A prescaler factor of zero corresponds to “no clock.” The “no
clock” condition is the UART power down mode, in which the
UART clock is turned off to reduce power consumption.
Software must select the “no clock” condition before enter-
ing a new baud rate. Otherwise, it could cause incorrect
data to be received or transmitted. The UnPSR register
must contain a value other than zero when an external clock
is used at CKX.
22.2.7 Interrupts
The UART is capable of generating interrupts on:
„ Receive Buffer Full
„ Receive Error
„ Transmit Buffer Empty
00010
1.5
00011
2
00100
2.5
00101
3
00110
3.5
00111
4
01000
4.5
01001
5
01010
5.5
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