CP3BT26 Datasheet, PDF (128/278 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth-R, USB, and CAN Interfaces

19.10 CAN CONTROLLER REGISTERS
Table 51 lists the CAN module registers.
Table 51 CAN Controller Registers
Name
Address
Description
19.10.1 Buffer Status/Control Register (CNSTAT)
The buffer status (ST), the buffer priority (PRI), and the data
length code (DLC) are controlled by manipulating the con-
tents of the Buffer Status/Control Register (CNSTAT). The
CPU and CAN module have access to this register.
CNSTAT
CGCR
CTIM
See
Table 50.
CAN Buffer Status/
Control Register
0E F100h
CAN Global
Configuration Register
0E F102h CAN Timing Register
15
12 11
87
43
0
DLC
Reserved
PRI
ST
0
R/W
GMSKX
GMSKB
BMSKX
BMSKB
CIEN
CIPND
CICLR
0E F104h Global Mask Register _ST
0E F106h Global Mask Register
0E F108h Basic Mask Register
0E F10Ah Basic Mask Register
0E F10Ch
CAN Interrupt
Enable Register
0E F10Eh
CAN Interrupt
Pending Register
0E F110h
CAN Interrupt
Clear Register
The Buffer Status field contains the status in-
formation of the buffer as shown in Table 52.
This field can be modified by the CAN module.
The ST0 bits acts as a buffer busy indication.
When the BUSY bit is set, any write access to
the buffer is disabled with the exception of the
lower byte of the CNSTAT register. The CAN
module sets this bit if the buffer data is cur-
rently copied from the hidden buffer or if a
message is scheduled for transmission or is
currently transmitting. The CAN module al-
ways clears this bit on a status update.
CICEN
0E F112h
CAN Interrupt Code
Enable Register
CSTPND
0E F114h
CAN Status
Pending Register
CANEC
CEDIAG
0E F116h
0E F118h
CAN Error
Counter Register
CAN Error
Diagnostic Register
CTMR
0E F11Ah CAN Timer Register
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