CP3BT26 Datasheet, PDF (253/278 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth-R, USB, and CAN Interfaces

30.11 MICROWIRE/SPI TIMING
Table 88 Microwire/SPI Signals
Symbol Figure
Description
Reference
Microwire/SPI Input Signals
t_MSKh
t_MSKl
t_MSKp
t_MSKh
t_MSKs
t_MWCSh
t_MWCSs
t_MDIh
t_MDIs
120 Microwire Clock High
At 2.0V (both edges)
120 Microwire Clock Low
At 0.8V (both edges)
120
Microwire Clock Period
121
SCIDL bit = 0; Rising Edge
(RE) MSK to next RE MSK
SCIDL bit = 1; Falling Edge
(FE) MSK to next FE MSK
120 MSK Hold (slave only)
After MWCS goes inactive
120 MSK Setup (slave only)
Before MWCS goes active
120
MWCS Hold (slave only)
121
SCIDL bit = 0: After FE
MSK
SCIDL bit = 1: After RE
MSK
120
MWCS Setup (slave only)
121
SCIDL bit = 0: Before RE
MSK
SCIDL bit = 1: Before FE
MSK
120
Microwire Data In Hold (master)
122
Normal Mode: After RE
MSK
Alternate Mode: After FE
MSK
120
Microwire Data In Hold (slave)
122
Normal Mode: After RE
MSK
Alternate Mode: After FE
MSK
120
Microwire Data In Setup
122
Normal Mode: Before RE
MSK
Alternate Mode: Before FE
MSK
Microwire/SPI Output Signals
t_MSKh
t_MSKl
t_MSKp
t_MSKd
t_MDOf
t_MDOh
t_MDOnf
120 Microwire Clock High
At 2.0V (both edges)
120 Microwire Clock Low
At 0.8V (both edges)
120
Microwire Clock Period
121
SCIDL bit = 0: Rising Edge
(RE) MSK to next RE MSK
SCIDL bit = 1: Falling Edge
(FE) MSK to next FE MSK
120
MSK Leading Edge Delayed (master
only)
Data Out Bit #7 Valid
120
Microwire Data Float ^b
(slave only)
After RE on MWCS
120
Microwire Data Out Hold
121
Normal Mode: After FE
MSK
Alternate Mode: After RE
MSK
124 Microwire Data No Float (slave only) After FE on MWCS
Min (ns)
80
80
200
40
80
40
80
0
40
80
40
40
100
0.5 t_MSK
-
0.0
0
Max (ns)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5 t_MSK
25
-
25
253
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