CP3BT26 Datasheet, PDF (169/278 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth-R, USB, and CAN Interfaces

Table 70 UART Registers
Name
U3OVR
U3MDSL2
U3SPOS
Address
FF F270h
FF F272h
FF F274h
Description
UART3 Oversample
Rate Register
UART3 Mode Select
Register 2
UART3 Sample
Position Register
22.3.4 UART Baud Rate Divisor (UnBAUD)
The UnBAUD register is a byte-wide, read/write register that
contains the lower eight bits of the baud rate divisor. The
register contents are unknown at power-up and are left un-
changed by a reset operation. The register format is shown
below.
7
0
UDIV7:0
22.3.1 UART Receive Data Buffer (UnRBUF)
UDIV7:0
The UnRBUF register is a byte-wide, read/write register
used to receive each data byte.
7
0
The Baud Rate Divisor field holds the eight
lowest-order bits of the UART baud rate divi-
sor used in the second stage of the two-stage
divider chain. The three most significant bits
are held in the UnPSR register. The divisor
value used is (UDIV[10:0] + 1).
URBUF
22.3.5 UART Frame Select Register (UnFRS)
22.3.2 UART Transmit Data Buffer (UnTBUF)
The UnTBUF register is a byte-wide, read/write register
used to transmit each data byte.
The UnFRS register is a byte-wide, read/write register that
controls the frame format, including the number of data bits,
number of stop bits, and parity type. This register is cleared
upon reset. The register format is shown below.
7
6
54
3
2
10
7
0
Reserved UPEN UPSEL UXB9 USTP UCHAR
UnTBUF
22.3.3 UART Baud Rate Prescaler (UnPSR)
UCHAR
The UnPSR register is a byte-wide, read/write register that
contains the 5-bit clock prescaler and the upper three bits of
the baud rate divisor. This register is cleared upon reset.
The register format is shown below.
7
3
2
0
USTP
UPSC
UDIV10:8
UPSC
UDIV10:8
The Prescaler field specifies the prescaler val-
ue used for dividing the System Clock in the
first stage of the two-stage divider chain. For
the prescaler factors corresponding to each 5-
bit value, see Table 69.
The Baud Rate Divisor field holds the three
most significant bits (bits 10, 9, and 8) of the
UART baud rate divisor used in the second
stage of the two-stage divider chain. The re-
maining bits of the baud rate divisor are held
in the UnBAUD register.
UXB9
UPSEL
The Character Frame Format field selects the
number of data bits per frame, not including
the parity bit, as follows:
00 – 8 data bits per frame.
01 – 7 data bits per frame.
10 – 9 data bits per frame.
11 – Loop-back mode, 9 data bits per frame.
The Stop Bits bit specifies the number of stop
bits transmitted in each frame. If this bit is 0,
one stop bit is transmitted. If this bit is 1, two
stop bits are transmitted.
0 – One stop bit per frame.
1 – Two stop bits per frame.
The Transmit 9th Data Bit holds the value of
the ninth data bit, either 0 or 1, transmitted
when the UART is configured to transmit nine
data bits per frame. It has no effect when the
UART is configured to transmit seven or eight
data bits per frame.
The Parity Select field selects the treatment of
the parity bit. When the UART is configured to
transmit nine data bits per frame, the parity bit
is omitted and the UPSEL field is ignored.
00 – Odd parity.
01 – Even parity.
10 – No parity, transmit 1 (mark).
11 – No parity, transmit 0 (space).
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