CP3BT26 Datasheet, PDF (177/278 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with Bluetooth-R, USB, and CAN Interfaces

23.2 MASTER MODE
In Master mode, the MSK pin is an output for the shift clock,
MSK. When data is written to the MWDAT register, eight or
sixteen MSK clocks, depending on the mode selected, are
generated to shift the 8 or 16 bits of data, and then MSK
goes idle again. The MSK idle state can be either high or
low, depending on the SCIDL bit.
MSK
Shift
Out
End of Transfer
Data Out
MSB
MSB - 1
MSB - 2
Bit 1
Bit 0
(LSB)
Data In
Sample
Point
MSB
MSB - 1
MSB - 2
Bit 1
Bit 0
(LSB)
Figure 85. Normal Mode (SCIDL = 0)
DS069
MSK
Data Out
Data In
Shift
Out
MSB
Sample
Point
MSB
MSB - 1
MSB - 1
MSB - 2
MSB - 2
End of Transfer
Bit 1
Bit 1
Bit 0
(LSB)
Bit 0
(LSB)
Figure 86. Normal Mode (SCIDL = 1)
DS070
MSK
Shift
Out
End of Transfer
Data Out
Data In
MSB
Sample
Point
MSB
MSB - 1
MSB - 1
MSB - 2
MSB - 2
Bit 1
Bit 1
Bit 0
(LSB)
Bit 0
(LSB)
Figure 87. Alternate Mode (SCIDL = 0)
DS071
MSK
Shift
Out
End of Transfer
Data Out
Data In
MSB
Sample
Point
MSB
MSB - 1
MSB - 1
MSB - 2
MSB - 2
Bit 1
Bit 1
Figure 88. Alternate Mode (SCIDL = 1)
Bit 0
(LSB)
Bit 0
(LSB)
DS072
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