MC68HC05F8 Datasheet, PDF (78/126 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor(HCMOS) microcontroller unit

Freescale Semiconductor, Inc.
CIE - Encoding Complete Interrupt Enable Bit
1 (set) – Enable encoding complete interrupt. If this bit is set, interrupt is
generated when the NCC flag is set.
0 (clear) – Disable the encoding complete interrupt.
DCE - Decoder Enable
1 (set) – Enable the decoder.
0 (clear) – Disable the decoder. When this bit is cleared, the decoder is reset,
receive and decode function is disabled.
DIE - Decode Interrupt Enable
1 (set) – Enable the decoder interrupt. If this bit is set, interrupt is generated
when the DCF or OVF flag is set.
0 (clear) – Disable the decoder interrupt.
BR1 & BR0 - Bit Rate Select
These two bits are used to select the transfer bit rate.
8
BR1 BR0
Bit Cycle
Bit rate (3.579MHz crystal)
0
0
1/8 (E/372)
601
0
1
1/4 (E/372)
1203
1
0
1/2 (E/372)
2405
1
1
E/372
4810
“bit” refers to bit unit in NRZ format, i.e. one bit is twice the bit
unit in Manchester format. E = internal bus clock
8.3.2 MANCD Status Register
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$2C NCM NCC DCF OVF
1100 ----
NCM - Encoder Data Register Empty Flag
The Encoder Data register empty flag is set to indicate the contents of the Encoder Data register
have been transferred to the encode data shift register. If the NCM bit is clear, it indicates that the
transfer has not yet occurred and a write to the Encode Data register will overwrite the previous
value. This bit is cleared by accessing the MANCD status register (with NCM set), followed by
writing to the Encode Data register. Reset sets the NCM bit.
MOTOROLA
8-8
MANCHESTER ENCODER/DECODER
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TPG
MC68HC05F8