MC68HC05F8 Datasheet, PDF (54/126 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor(HCMOS) microcontroller unit

Freescale Semiconductor, Inc.
TOIE - Timer Overflow Interrupt Enable
1 (set) – Timer Overflow interrupt enabled.
0 (clear) – Timer Overflow interrupt disabled.
IEDG - Input Edge
1 (set) – TCAP is positive-going edge sensitive.
0 (clear) – TCAP is negative-going edge sensitive.
When IEDG is set, a positive-going edge on the TCAP pin will trigger a transfer of the free-running
counter value to the input capture registers. When clear, a negative-going edge triggers the
transfer.
OLVL - Output Level Voltage Latch
6
1 (set) – High output on TCMP pin if counter compare is true.
0 (clear) – Low output on TCMP pin if counter compare is true.
There is a bit in the Event Enable register which may be used to disable and enable the
programmable timer.
Event Enable Register
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$16 TIMHA INTE1 INTE2 0
0
0
0
0 0000 0000
TIMHA - Timer A Enable/Disable
1 (set) – Timer inhibit
0 (clear) – Enable timer (default at reset)
6.1.5 Timer A Status Register (TSR)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on Reset
$19 ICF OCF TOF
0
0
0
0
0 uuu0 0000
The Timer Status register ($19) contains the status bits for the above three interrupt conditions -
ICF, OCF, TOF.
Accessing the timer status register satisfies the first condition required to clear the status bits. The
remaining step is to access the register corresponding to the status bit.
MOTOROLA
6-6
TIMERS
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MC68HC05F8