MC68HC05F8 Datasheet, PDF (57/126 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor(HCMOS) microcontroller unit

Freescale Semiconductor, Inc.
INTERNAL
PROCESSOR
CLOCK
T00
INTERNAL ^T01
TIMER
CLOCKS _T10
T11
COUNTER
(16 BIT)
$F455
OUTPUT COMPARE
REGISTER
$F456
Note 1
CPU writes $F457
$F457
$F458
$F457
COMPARE REGISTER
LATCH
OUTPUT COMPARE
Flag (OCF) and TCMP
Note 1
Note 2
Note: 1. The CPU write to the compare registers may take place at any time, but a compare only occurs at
the timer state T01. Thus a 4-cycle difference may exist between the write to the compare register
and the actual compare.
2. The output compare flag is set at the timer state T11 that follows the comparison match ($F547 in
this example).
Figure 6-4 Timer State Timing Diagram for Output Compare
$F459
6
INTERNAL
PROCESSOR
CLOCK
T00
INTERNAL ^T01
TIMER
CLOCKS _T10
T11
COUNTER
(16 BIT)
$FFFE
$FFFF
$0000
TIMER
OVERFLOW
FLAG (TOF)
Note: The TOF bit is set at timer state T11 (transition of counter from $FFFF to $0000).
It is cleared by a read of the timer status register during the internal processor
clock high time followed by a read of the counter low register.
$0001
Figure 6-5 Timer State Diagram for Timer Overflow
MC68HC05F8
TIMERS
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$0002
TPG
MOTOROLA
6-9