MC68HC05F8 Datasheet, PDF (37/126 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor(HCMOS) microcontroller unit

Freescale Semiconductor, Inc.
5
INTERRUPTS
The MC68HC05F8 is capable of handling eight types of interrupt, seven hardware and one
software. The interrupt mask bit (“I” bit in the Condition Code register), if set, masks all interrupts
5
except the software interrupt, SWI. Interrupts such as IRQ, Timers, and MANCD have several
flags which will cause the interrupt. Interrupt flags are found in “read only” status registers, while
their enables are in associated control registers. They are never mixed in the same register. If the
enable bit is “0”, it masks the interrupt from occurring but does not inhibit the flag from being set.
A reset clears all enable bits. The general sequence for clearing an interrupt is a software
sequence of reading the status register while the flag is set followed by a read or write of an
associated register. When any of these interrupts occur, and if enabled, normal processing is
suspended at the end of the current instruction execution. The state of the machine is pushed onto
the stack (see Figure 5-1 for stacking order) and the appropriate vector points to the starting
address of the interrupt service routine (see Table 5-1). Also, the interrupt mask bit in the condition
code register is set. This masks further interrupts. At the completion of the service routine, the
software normally contains an RTI instruction which, when executed, restores the machine state
and continues executing the interrupted program. Figure 5-2 is a flowchart showing the program
flow and interrupt priority for hardware interrupts.
Note:
The interrupt mask bit (I bit) will be cleared if and only if the corresponding bit stored
on the stack is zero.
MC68HC05F8
INTERRUPTS
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5-1