MC68HC05F8 Datasheet, PDF (66/126 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor(HCMOS) microcontroller unit

Freescale Semiconductor, Inc.
MASTER
8-BIT SHIFT REGISTER
SDI
SDO
SPI
CLOCK GENERATOR
SCK
(447.5 KHz)
SLAVE
SDO
8-BIT SHIFT REGISTER
SDI
SCK
Figure 7-1 SPI Master-Slave Interconnection
SCK
7
SDO
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SDI
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
112ns 112ns
Figure 7-2 SPI Port Timing
7.2.1 Serial Clock (SCK)
The state of SCK between transmissions must be logic “1”. The first falling edge of SCK signals
the beginning of a transmission. At this time the MSB bit of received data is accepted at the
SDI pin and the MSB bit of transmitted data is presented at the SDO pin. Data is captured at the
SDI pin on the rising edge of SCK. Subsequent falling edges shift the data, and accept the next
received data bit at SDI pin, and present the next transmitted data bit at SDO pin. The transmission
is ended upon the receipt of the LSB bit.
In Master Mode, the format is identical except that the SCK pin is an output and the shift clock now
originates internally. The Master Mode transmission frequency is fixed at E/4.
Care should be taken when enabling the SPI; additional clock edges may be present when the
port is switched from standard I/O to SPI.
MOTOROLA
7-2
SERIAL PERIPHERAL INTERFACE
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TPG
MC68HC05F8