MC68HC05F8 Datasheet, PDF (51/126 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor(HCMOS) microcontroller unit

Freescale Semiconductor, Inc.
The key element in the programmable timer is a 16-bit, free-running counter or counter register,
preceded by two prescalers. The first stage programmable prescaler provides a slow timer clock
by dividing the internal processor clock either by 1, 4, 8, or 16. The second stage is a fixed divide
by four prescaler. See Figure 6-1 and Table 6-1 for prescaler values. The counter is incremented
during the low portion of the internal bus clock, and the counting can be inhibited by setting the
TIMHA bit in the Event Enable register (bit 7 of address $16). Software can read the counter at
any time without affecting its value.
System Option Register
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$35
- TCSA1 TCSA0 INTN1 INTN2 -
-
- -000 0---
Table 6-1 Timer A Clock Frequency Selection
TCSA1
TCSA0
Clock Frequency of Timer A
6
0
0
E/4
0
1
E / 16
1
0
E / 32
1
1
E / 64
Where E = internal bus clock
The double-byte, free-running counter can be read from either of two locations, $1E & $1F
(counter register) or $20 & $21 (counter alternate register). Reading only the least significant byte
(LSB) of the free-running counter ($1F or $21) receives the count value at the time of the read. If
the most significant byte (MSB) ($1E or $20) is read first, the LSB ($1F or $21) is transferred to a
buffer. This buffer value remains fixed after the first MSB read, even if the MSB is read several
times. This buffer is accessed when the LSB ($1F or $21) is read, and thus, completes a read
sequence of the complete counter value.
Reading the timer counter register low byte after reading the timer status register clears the timer
overflow flag (TOF), but reading the counter alternate register does not affect TOF. Therefore, the
counter alternate register can be read any time without risk of missing timer overflow interrupts
due to a cleared TOF.
The free-running counter is preset to $FFFC during reset and is always a read-only register.
During a power-on reset, the counter is also preset to $FFFC and begins running after the
oscillator start-up delay. The value in the free-running counter repeats every (262144÷R_TB)
internal bus clock cycles (t_CYC). R_TB is the ratio of timer clock to bus clock frequency, and is
dependent on the values of TCSA0 and TCSA1 bits. TOF is set when the counter overflows (from
$FFFF to $0000); this will cause an interrupt if TOIE in the Timer Control register is set (bit 5 of
address $18).
MC68HC05F8
TIMERS
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6-3