MC68HC05F8 Datasheet, PDF (60/126 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor(HCMOS) microcontroller unit

Freescale Semiconductor, Inc.
the time of the read. If the most significant byte (MSB) ($25 or $27) is read first, the LSB ($26 or
$28) is transferred to a buffer. This buffer value remains fixed after the first MSB read, even if the
MSB is read several times. This buffer is accessed when the LSB ($26 or $28) is read, and thus,
completes a read sequence of the complete counter value.
6.2.4 Timer B Preset Register
– Timer B Preset Register
High byte - $23, Low byte - $24
On the low to high transition of the TMBE bit, the reloadable timer is loaded with the value set in
this 16-bit register.
6.2.5 Timer B Control Status Register
6
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$22 TMBE TOIE
TCSB1 TCSB0 TUF 00-- -000
TMBE - Timer B Enable/Disable
1 (set) – Timer B enabled.
0 (clear) – Timer B disabled.
Upon reset, this bit is cleared and the driving clock of timer B is inhibited, a low to high transition
of this bit loads the timer B counter with the contents of the preset register and activates the driving
clock.
TBOIE - Timer B Time-out Interrupt Enable/Disable
1 (set) – Timer B time-out interrupt enabled.
0 (clear) – Timer B time-out interrupt disabled.
When this bit is set, timer B time out interrupt will occur if the time out flag (TUF) is set; otherwise,
time out interrupt is disabled.
TCSB1, TCSB0 - Timer B Clock Frequency Select
These two bits are used to select the frequency of timer B driving clock. See Table 6-2.
TUF - Timer B Underflow Flag
This bit is set when the counter of Timer B rolls from $0001 to $0000. It should be cleared by
software in the timer B interrupt service routine.
MOTOROLA
6-12
TIMERS
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MC68HC05F8