MC68HC05F8 Datasheet, PDF (69/126 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor(HCMOS) microcontroller unit

Freescale Semiconductor, Inc.
status register bit (SPIF) is set to a logic one. It does not inhibit the setting of a status bit. The
SPIE bit is cleared by reset.
SPE - Serial Peripheral Enable
When set, this bit enables the Serial I/O Port and initializes the Port D DDR such that PD5 (SDO)
is output, PD6 (SDI) is input and PD7 (SCK) is input (Slave Mode only). The Port D DDR can be
subsequently altered as the application requires and the Port D data register (except for PD5) can
be manipulated as usual, however these actions could affect the transmitted or received data.
When SPE is cleared, Port D reverts to standard parallel I/O without affecting the Port D data
register or DDR. SPE can be read or written any time, but clearing SPE while a transmission is in
progress will abort the transmission, reset the bit count and return Port D to its normal I/O function.
Reset clears this bit.
MSTR - Master Bit
When set, this bit configures the SPI for Master Mode. This means that the transmission is initiated
by a write to the data register and the SCK pin becomes an output providing a synchronous data
clock at a fixed rate of E clock divided by 4. While the device is in Master Mode, the SDO and SDI
pins do not change function. These pins behave exactly as they would in Slave Mode. Reset clears
this bit and configures the SPI for Slave operation. MSTR may be set at any time regardless of the
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state of SPE. Clearing MSTR will abort any transmission in progress.
7.4.2 SPI Status Register (SPSR)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$11 SPIF DCOL
00-- ----
SPIF - Serial Peripheral Interface Flag
The serial peripheral data transfer flag bit notifies the user that a data transfer between the device
and an external device has been completed. With the completion of the data transfer, SPIF is set,
and if SPIE is set, a serial peripheral interrupt (SPI) is generated. During the clock cycle that SPIF
is being set, a copy of the received data byte in the shift register is moved to a buffer. When the
data register is read, it is the buffer that is read.
The transfer of data is initiated by the master device writing its serial peripheral data register.
Clearing the SPIF bit is accomplished by a software sequence of accessing the serial peripheral
status register while SPIF is set and followed by a write to or a read of the serial peripheral data
register. While SPIF is set, all writes to the serial peripheral data register are inhibited until the
serial peripheral status register is read. This occurs in the master device. In the slave device, SPIF
can be cleared before the second SPIF in order to prevent an overrun condition. The SPIF bit is
cleared by reset.
MC68HC05F8
SERIAL PERIPHERAL INTERFACE
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