MC68HC05F8 Datasheet, PDF (42/126 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor(HCMOS) microcontroller unit

Freescale Semiconductor, Inc.
The interrupt logic recognizes negative edge transitions and pulses (special case of negative
edges) on the external interrupt lines. Figure 5-3 shows both a block diagram and timing for the
interrupt lines (IRQ1, IRQ2) to the processor. The first method is used if pulses on the interrupt
line are spaced far enough apart to be serviced. The minimum time between pulses is equal to
the number of cycles required to execute the interrupt service routine plus 21 cycles. Once a pulse
occurs, the next pulse should not occur until the MCU software has exited the routine (an RTI
occurs). The second configuration shows several interrupt lines wired-OR to perform the interrupt
at the processor. Thus, if the interrupt lines remain low after servicing one interrupt, the next
interrupt is recognized.
Note: The internal interrupt latch is cleared in the first part of the service routine; therefore,
5
one (and only one) external interrupt pulse could be latched during t_ILIL and serviced
as soon as the I bit is cleared.
5.3.1 External Interrupt Triggering Options (INTN1 & INTN2)
System Option Register
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$35
TCSA1 TCSA0 INTN1 INTN2
-000 0---
INTN1
1 (set) – Negative edge triggering for IRQ1 only.
0 (clear) – Level and negative edge triggering for IRQ1.
INTN2
1 (set) – Negative triggering for IRQ2 only.
0 (clear) – Level and negative edge triggering for IRQ2.
5.3.2 External Interrupt Enable (INTE1 & INTE2)
Event Enable Register
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$16 TIMHA INT1E INT2E
000- ----
INT1E
1 (set) – External interrupt IRQ1 enabled.
0 (clear) – External interrupt IRQ1 disabled.
MOTOROLA
5-6
INTERRUPTS
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MC68HC05F8