MC68HC05F8 Datasheet, PDF(47/126 Page) Motorola, Inc – High-density complementary metal oxide semiconductor(HCMOS) microcontroller unit

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MC68HC05F8 Datasheet, PDF (47/126 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor(HCMOS) microcontroller unit

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Freescale Semiconductor, Inc.

5.8

Manchester Coder (MANCD) Interrupt

A Manchester Coder interrupt occurs when one of the interrupt ï¬ags in the MANCD Status register

(location $2C) is set, provided the interrupt mask bit in the Condition Code register is cleared and

the enable bit in the MANCD Control register ($2B) is enabled. When the interrupt is recognized,

the current state of the CPU is pushed onto the stack and the interrupt mask bit in the condition

code register is set. This masks any further interrupt until the present one is serviced. The MANCD

interrupt causes the program counter to vector to memory location $FFF2 and $FFF3 which

contains the starting address of the interruptâs service routine.

Software in the MANCD interrupt service routine must determine the priority and the cause of the

MANCD interrupt by examining the interrupt ï¬ags located in the MANCD Status register.

There are four interrupt ï¬ags associated with MANCD interrupts:

Address bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

State

on reset

$2C NCM NCC DCF OVF

1100 ----

NCM - Encoder Data Register Empty Flag

1 (set) â Encoder Data register is empty.

0 (clear) â Encoder Data register is not empty.

This bit is cleared by accessing the MANCD Status register (with NCM set), followed by writing to

the Encoder Data register.

NCC - Encoding Completion Flag

1 (set) â Encoder is disabled (NCE=0) or, NCE=1 and transmission of the

data in the shift register is completed.

0 (clear) â Transmission of data in process.

This bit is cleared by writing to the Encoder Data register when NCE bit is set.

DCF - Decoder Data Register Full Flag

1 (set) â One byte of data received with end pattern veriï¬ed.

0 (clear) â Decoder Data register not full.

This bit is cleared when the MANCD Status register is accessed (with DCF set) followed by a read

of the Decoder Data register, or by clearing the DCE bit.

OVF - Overrun Flag

1 (set) â An overrun has occurred.

0 (clear) â An overrun has not occurred.

MC68HC05F8

INTERRUPTS

For More Information On This Product,

Go to: www.freescale.com

TPG

MOTOROLA

5-11

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