MC68HC05F8 Datasheet, PDF (35/126 Pages) Motorola, Inc – High-density complementary metal oxide semiconductor(HCMOS) microcontroller unit

Freescale Semiconductor, Inc.
Table 4-1 Reset Action on Internal Circuit
DEFAULT CONDITIONS AFTER RESET
1
Timer A not inhibited (TIMHA bit cleared).
2
Timer A prescaler reset to zero state.
3
Timer A counter configures to $FFFC.
4
Timer A output compare (TCMP) bit is reset to zero.
5
Timer A clock=internal bus clock ÷ 4 (TCSA1=TCSA0=0).
6
All timer A interrupt enable bits cleared (ICIE, OCIE, and TOIE) to disable timer interrupts.
The OLVL timer bit is also cleared by reset.
4
7
Timer B is disabled (TMBE bit cleared).
8
Timer B prescaler reset to zero (TCSB0=TCSB1=0).
9
All data direction registers cleared to zero (default as inputs).
10
Stack pointer configured to $00FF.
11
Internal address bus forced to restart vector ($FFFE-$FFFF).
12
I bit of condition code register set to logic 1.
13*
STOP latch cleared.
14
WAIT latch cleared.
15
External interrupt latch cleared (INTF1=INTF2=0).
16
External interrupt enable bits cleared (INTE1 & INTE2).
17
SPI disabled (serial output enable control bit SPE=0).
Other SPI bits cleared are SPIE, MSTR, SPIF, and DCOL.
18
SPI system configured to slave mode (MSTR=0).
19
Keyboard interrupt enabled (KEYE) and keyboard interrupt flag (KEYF) bits are cleared.
20
Disable MANCD (NCD=DCE=0).
21
Disable tone generation in DMG (TGER=TGEC=0).
22
Place DMG in DTMF mode (MS1=MS0=0).
23
Watchdog timer is inhibited (WDTE=0), kill function is disabled (KWDT=0).
24
If reset is by POR, set POR bit.
* Indicates that time-out still occurs.
Listed numbers do not represent order of occurrence.
MC68HC05F8
RESETS
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MOTOROLA
4-3