MC68HC711K4CFN4 Datasheet, PDF (69/80 Pages) Motorola, Inc – 8-Bit Microcontroller

NOTE
Control bits [7:4] in TMSK2 correspond bit for bit with flag bits [7:4] in TFLG2. Ones
in TMSK2 enable the corresponding interrupt sources.
Bits [3:2] —Not implemented
Always read zero
PR[1:0] —Timer Prescaler Select
In normal modes, PR1 and PR0 can only be written once, and the write must occur within 64 cycles
after reset. Refer to Table 10 for specific timing values.
PR[1:0]
00
01
10
11
Prescaler
1
4
8
16
TFLG2 —Timer Interrupt Flag 2
Bit 7
6
5
4
3
2
TOF
RTIF PAOVF PAIF
—
—
RESET:
0
0
0
0
0
0
Clear flags by writing a one to the corresponding bit position(s).
TOF —Timer Overflow Flag
Set when TCNT changes from $FFFF to $0000
RTIF —Real-Time (Periodic) Interrupt Flag
0 = No RTI interrupt
1 = RTI interrupt request pending
PAOVF —Pulse Accumulator Overflow Flag
Refer to 11 Pulse Accumulator.
PAIF —Pulse Accumulator Input Edge Flag
Refer to 11 Pulse Accumulator.
Bits [3:0] —Not implemented
Always read zero
PACTL —Pulse Accumulator Control
Bit 7
6
5
4
3
—
PAEN PAMOD PEDGE
—
RESET:
0
0
0
0
0
2
I4/O5
0
Bit 7 —Not implemented
Always read zero
PAEN —Pulse Accumulator System Enable
Refer to 11 Pulse Accumulator.
PAMOD —Pulse Accumulator Mode
Refer to 11 Pulse Accumulator.
1
—
0
1
RTR1
0
$0025
Bit 0
—
0
$0026
Bit 0
RTR0
0
M68HC11 K Series
MC68HC11KTS/D
MOTOROLA
69