MC68HC711K4CFN4 Datasheet, PDF (11/80 Pages) Motorola, Inc – 8-Bit Microcontroller

2 Operating Modes
The M68HC11 K-series MCUs have four modes of operation that directly affect the address space.
These modes are described as follows.
2.1 Single-Chip Operating Mode
In single-chip operating mode, the M68HC11 K-series MCUs are stand-alone microcontrollers with no
external address or data bus. Addressing range is 64 Kbytes and is limited to on-chip resources. Refer
to the memory map diagram.
2.2 Expanded Operating Mode
In expanded operating mode, the MCU has a 64 Kbyte address range and, using the expansion bus,
can access external resources within the 64 Kbyte space. This space includes the same on-chip mem-
ory addresses used for single-chip mode, in addition to addressing capabilities for external peripheral
and memory devices. Addressing beyond 64 Kbytes is available only in expanded mode using the on-
chip, register-based memory mapping logic. The additional address lines for memory expansion
(XA[18:13]) are implemented as alternate functions of port G. The expansion bus (external address and
data buses) is made up of ports B, C, and F, and the R/W signal. In expanded operating mode, high
order address bits are output on the port B pins, low order address bits on the port F pins, and the data
bus on port C. Refer to the memory map diagram.
2.3 Bootstrap Mode
Bootstrap mode allows special-purpose programs to be loaded into internal RAM. The MCU contains
448 bytes of bootstrap ROM which is enabled and present in the memory map only when the device is
in bootstrap mode. The bootstrap ROM contains a program which initializes the SCI and allows the user
to download up to 768 bytes of code into on-chip RAM. After a four-character delay, or after receiving
the character for address $037F, control passes to the loaded program at $0080. Refer to the memory
map diagram. Refer also to Application Note M68HC11 Bootstrap Mode (AN1060/D).
2.4 Special Test Mode
Special test mode is used primarily for factory testing. In this operating mode, ROM/EPROM is removed
from the address space and interrupt vectors are accessed externally at $BFC0–$BFFF.
2.5 Mode Selection
Operating modes are selected by a combination of logic levels applied to two input pins (MODA and
MODB) during reset. The logic level present (at the rising edge of reset) on these inputs is reflected in
bits in the HPRIO register. After reset, the operating mode may be changed according to the table con-
tained in the description of the HPRIO register.
The functions of two features that are enabled by bits in OPT2 register are dependent upon the operat-
ing mode. LIR driven is enabled with the LIRDV bit. Internal read visibility/not E is enabled with the
IRVNE bit. Refer to the OPT2 register description that follows HPRIO.
HPRIO —Highest Priority I-Bit Interrupt and Miscellaneous
$003C
Bit 7
6
5
4
3
2
1
Bit 0
RBOOT* SMOD* MDA* PSEL4 PSEL3 PSEL2 PSEL1 PSEL0
RESET:
0
0
0
0
0
1
1
0
Single Chip
0
0
1
0
0
1
1
0
Expanded
1
1
0
0
0
1
1
0
Bootstrap
0
1
1
0
0
1
1
0 Special Test
*The reset values of RBOOT, SMOD, and MDA depend on the mode selected at power up.
M68HC11 K Series
MC68HC11KTS/D
MOTOROLA
11