MC68HC711K4CFN4 Datasheet, PDF (36/80 Pages) Motorola, Inc – 8-Bit Microcontroller

$0000
$1000
$00000
$02000
$04000
WINDOW 1
$06000 $08000
$0A000
$0C000
$0E000
$4000
$6000
CHIP SELECT 1
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
XA[15:13]= XA[15:13]= XA[15:13]= XA[15:13]= XA[15:13]= XA[15:13]= XA[15:13]= XA[15:13]=
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
$01FFF $03FFF $05FFF $07FFF $09FFF $0BFFF $0DFFF $0FFFF
$A000
INTERNAL
EPROM
$FFFF
PGAR = $07 XA[15:13]
MMWBR = $04 WINDOW 1 @ $4000,
WINDOW 2 DISABLED
MMSIZ = $41 WINDOW 1 = 8 KBYTES,
WINDOW 2 DISABLED
CSCTL = $00 NO I/O OR PROGRAM CHIP SELECTS
GPCS1A = $00 GEN. PURPOSE CHIP SELECT 1 FROM $00000
GPSC1C = $06 64 KBYTE RANGE (8 X 8K)
GPCS2A = $00 N/A
GPCS2C = $00 GEN. PURPOSE CHIP SELECT 2 DISABLED
Figure 7 Memory Expansion Example 1
This example is a system consisting of the MCU, a single 27C512-type memory device as in the previ-
ous example, and two 6226-type memory devices as well. This system uses two chip selects and has
two windows. For purposes of explanation, the setup of the first window is identical to the previous ex-
ample. In addition, a second window consisting of 16 banks of 16 Kbytes each uses the second chip
select signal. Window 1 contains 64 Kbytes of expanded memory pages, window 2 contains a total of
256 Kbytes of expanded memory. A total of five expansion address lines are used. Register values par-
ticular to this example are given below the diagram.
MOTOROLA
36
M68HC11 K Series
MC68HC11KTS/D