MC68HC711K4CFN4 Datasheet, PDF (46/80 Pages) Motorola, Inc – 8-Bit Microcontroller

PT —Parity Type
Refer to 7 Serial Communications Interface.
PORTE —Port E Data
$000A
Bit 7
6
5
4
3
2
1
Bit 0
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
RESET:
I
I
I
I
I
I
I
I
Alt. Pin
Func.:
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
DDRF —Data Direction Register for Port F
RESET:
Bit 7
DDF7
0
6
DDF6
0
5
DDF5
0
4
DDF4
0
3
DDF3
0
2
DDF2
0
1
DDF1
0
$0003
Bit 0
DDF0
0
DDF[7:0] —Data Direction for Port F
0 = Corresponding pin configured for input
1 = Corresponding pin configured for output
PORTF —Port F Data
$0005
Bit 7
6
5
4
3
2
1
Bit 0
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
S. Chip or
Boot:
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
RESET:
I
I
I
I
I
I
I
I
Expan. or
Test: ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
Reset state is mode dependent. In single-chip or bootstrap modes, port F is high-impedance input with
selectable internal pull-up resistors. In expanded or test modes, port F pins are low order address out-
puts and PORTF is not in the memory map.
PORTH —Port H Data
$007C
Bit 7
6
5
4
3
2
1
Bit 0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
RESET:
I
I
I
I
I
I
I
I
Alt. Pin CSPROG CSGP2 CSGP1
Func.:
CSIO
PW4
PW3
PW2
PW1
Port H pins reset to high-impedance inputs with selectable internal pull-up resistors. In expanded and
special test modes, reset also causes PH7 to be configured as CSPROG.
DDRH —Data Direction Register for Port H
$007D
RESET:
Bit 7
DDH7
0
6
DDH6
0
5
DDH5
0
4
DDH4
0
3
DDH3
0
2
DDH2
0
1
DDH1
0
Bit 0
DDH0
0
DDH[7:0] —Data Direction for Port H
0 = Bits set to zero to configure corresponding I/O pin for input only
1 = Bits set to one to configure corresponding I/O pin for output
MOTOROLA
46
M68HC11 K Series
MC68HC11KTS/D