MC68HC711K4CFN4 Datasheet, PDF (39/80 Pages) Motorola, Inc – 8-Bit Microcontroller

Vector Address
Interrupt Source
FFC0, C1 —FFD4, D5
FFD6, D7
FFD8, D9
FFDA, DB
FFDC, DD
FFDE, DF
FFE0, E1
FFE2, E3
FFE4, E5
FFE6, E7
FFE8, E9
FFEA, EB
FFEC, ED
FFEE, EF
FFF0, F1
FFF2, F3
FFF4, F5
FFF6, F7
FFF8, F9
FFFA, FB
FFFC, FD
FFFE, FF
Reserved
SCI Serial System
• SCI Receive Data Register Full
• SCI Receiver Overrun
• SCI Transmit Data Register Empty
• SCI Transmit Complete
• SCI Idle Line Detect
SPI Serial Transfer Complete
Pulse Accumulator Input Edge
Pulse Accumulator Overflow
Timer Overflow
Timer Input Capture 4/Output Compare 5
Timer Output Compare 4
Timer Output Compare 3
Timer Output Compare 2
Timer Output Compare 1
Timer Input Capture 3
Timer Input Capture 2
Timer Input Capture 1
Real Time Interrupt
IRQ
XIRQ Pin
Software Interrupt
Illegal Opcode Trap
COP Failure
Clock Monitor Fail
RESET
CCR Mask
Bit
—
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
X
None
None
None
None
None
Local Mask
—
RIE
RIE
TIE
TCIE
ILIE
SPIE
PAII
PAOVI
TOI
I4/O5I
OC4I
OC3I
OC2I
OC1I
IC3I
IC2I
IC1I
RTII
None
None
None
None
NOCOP
CME
None
Priority
(1 = High)
—
19
20
21
22
23
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
*
*
3
2
1
*Same level as an instruction
OPTION —System Configuration Options
$0039
Bit 7
6
5
4
3
2
1
Bit 0
ADPU CSEL IRQE* DLY*
CME FCME* CR1*
CR0*
RESET:
0
0
0
1
0
0
0
0
*Can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes.
ADPU —A/D Converter Power up
Refer to 9 Analog-to-Digital Converter.
CSEL —Clock Select
Refer to 9 Analog-to-Digital Converter.
IRQE —IRQ Select Edge Sensitive Only
0 = Low level recognition
1 = Falling edge recognition
DLY —Enable Oscillator Start-Up Delay on Exit from STOP
0 = No stabilization delay on exit from STOP
1 = Stabilization delay enabled on exit from STOP
M68HC11 K Series
MC68HC11KTS/D
MOTOROLA
39