MC68HC711K4CFN4 Datasheet, PDF (68/80 Pages) Motorola, Inc – 8-Bit Microcontroller

TMSK1 —Timer Interrupt Mask 1
$0022
Bit 7
6
5
4
3
2
1
Bit 0
OC1I
OC2I
OC3I
OC4I
I4/O5I
IC1I
IC2I
IC3I
RESET:
0
0
0
0
0
0
0
0
OC1I–OC4I —Output Compare x Interrupt Enable
If the OCxF flag bit is set while the OCxI enable bit is set, a hardware interrupt sequence is requested.
I4/O5I —Input Capture 4 or Output Compare 5 Interrupt Enable
When I4/O5 in PACTL is one, I4/O5I is the input capture 4 interrupt bit. When I4/O5 in PACTL is zero,
I4/O5I is the output compare 5 interrupt control bit.
IC1I–IC3I —Input Capture x Interrupt Enable
If the ICxF flag bit is set while the ICxI enable bit is set, a hardware interrupt sequence is requested.
TFLG1 —Timer Interrupt Flag 1
$0023
Bit 7
6
5
4
3
2
OC1F OC2F OC3F OC4F I4/O5F IC1F
RESET:
0
0
0
0
0
0
Clear flags by writing a one to the corresponding bit position(s).
1
IC2F
0
Bit 0
IC3F
0
OC1F–OC5F —Output Compare x Flag
Set each time the counter matches output compare x value
I4/O5F —Input Capture 4/Output Compare 5 Flag
Set by IC4 or OC5, depending on which function was enabled by I4/O5 of PACTL
IC1F–IC3F —Input Capture x Flag
Set each time a selected active edge is detected on the ICx input line
NOTE
Control bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Ones in TMSK1
enable the corresponding interrupt sources.
TMSK2 —Timer Interrupt Mask 2
Bit 7
6
5
4
3
TOI
RTII
PAOVI
PAII
—
RESET:
0
0
0
0
0
TOI —Timer Overflow Interrupt Enable
0 = Timer overflow interrupt disabled
1 = Timer overflow interrupt enabled
RTII —Real-Time Interrupt Enable
0 = RTIF interrupts disabled
1 = Interrupt requested when RTIF is set to one.
PAOVI —Pulse Accumulator Overflow Interrupt Enable
Refer to 11 Pulse Accumulator.
PAII —Pulse Accumulator Interrupt Enable
Refer to 11 Pulse Accumulator.
$0024
2
1
Bit 0
—
PR1
PR0
0
0
0
MOTOROLA
68
M68HC11 K Series
MC68HC11KTS/D