MC68HC711K4CFN4 Datasheet, PDF (40/80 Pages) Motorola, Inc – 8-Bit Microcontroller

CME —Clock Monitor Enable
0 = Clock monitor disabled; slow clocks can be used
1 = Slow or stopped clocks cause clock failure reset
FCME —Force Clock Monitor Enable
0 = Clock monitor follows the state of the CME bit
1 = Clock monitor circuit is enabled until next reset
CR[1:0] —COP Timer Rate Select
Refer to NOCOP bit in CONFIG register.
CR[1:0]
00
01
10
11
Table 6 COP Timer Rate Select (Timeout Period Length)
Rate
Selected
2¹⁵
2¹⁷
2¹⁹
2²¹
E=
XTAL = 8.0 MHz
Timeout
–0 ms, +16.4 ms
16.384 ms
65.536 ms
262.14 ms
1.049 sec
2.0 MHz
XTAL = 12.0 MHz
Timeout
–0 ms, +10.9 ms
10.923 ms
43.691 ms
174.76 ms
699.05 ms
3.0 MHz
XTAL = 16.0 MHz
Timeout
–0 ms, +8.2 ms
8.192 ms
32.768 ms
131.07 ms
524.29 ms
4.0 MHz
COPRST —Arm/Reset COP Timer Circuitry
$003A
Bit 7
6
5
4
3
2
1
Bit 0
7
6
5
4
3
2
1
0
RESET:
0
0
0
0
0
0
0
0
Write $55 (%01010101) to COPRST to arm COP watchdog clearing mechanism. Write $AA
(%10101010) to COPRST to reset COP watchdog. Refer to NOCOP bit in CONFIG register.
HPRIO —Highest Priority I-Bit Interrupt and Miscellaneous
$003C
Bit 7
6
5
4
3
2
1
Bit 0
RBOOT* SMOD* MDA* PSEL4 PSEL3 PSEL2 PSEL1 PSEL0
RESET:
—
—
—
0
0
1
1
0
*RBOOT, SMOD, and MDA reset depend on power-up initialization mode and can only be written in special mode.
RBOOT —Read Bootstrap ROM
Refer to 2 Operating Modes.
SMOD —Special Mode Select
Refer to 2 Operating Modes.
MDA —Mode Select A
Refer to 2 Operating Modes.
MOTOROLA
40
M68HC11 K Series
MC68HC11KTS/D