MC68HC711K4CFN4 Datasheet, PDF (58/80 Pages) Motorola, Inc – 8-Bit Microcontroller

SPR[2:0] —SPI Clock Rate Selects (SPR2 is located in OPT2 register)
SPR[2:0]
000
001
010
011
100
101
110
111
Table 8 SPI Clock Rate Selects
Divide
E Clock By
2
4
16
32
8
16
64
128
Frequency at
E = 2 MHz (Baud)
1.0 MHz
500 kHz
125 kHz
62.5 kHz
250 kHz
125 kHz
31.25 kHz
15.625 kHz
Frequency at
E = 3 MHz (Baud)
3.0 MHz
750 kHz
187.5 kHz
93.75 kHz
375 kHz
187.5 kHz
46.875 kHz
23.438 kHz
Frequency at
E = 4 MHz (Baud)
4.0 MHz
1.0 MHz
250 kHz
125 kHz
500 kHz
250 kHz
62.5 kHz
31.25 kHz
SPSR —Serial Peripheral Status Register
$0029
Bit 7
6
5
4
3
2
1
Bit 0
SPIF WCOL
—
MODF
—
—
—
—
RESET:
0
0
0
0
0
0
0
0
SPIF —SPI Transfer Complete Flag
This flag is set when an SPI transfer is complete (after eight SCK cycles in a data transfer). Clear this
flag by reading SPSR, then access SPDR.
0 = No SPI transfer complete or SPI transfer still in progress
1 = SPI transfer complete
WCOL —Write Collision Error Flag
This flag is set if the MCU tries to write data into SPDR while an SPI data transfer is in progress. Clear
this flag by reading SPSR, then access SPDR.
0 = No write collision error
1 = SPDR written while SPI transfer in progress
Bit 5 —Not implemented
Always reads zero
MODF —Mode Fault (Mode fault terminates SPI operation)
Set when SS is pulled low while MSTR = 1. Cleared by SPSR read followed by SPCR write.
0 = No mode fault error
1 = SS pulled low in master mode
Bits [3:0] —Not implemented
Always read zero
SPDR —SPI Data
$002A
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
SPI is double buffered in, single buffered out.
MOTOROLA
58
M68HC11 K Series
MC68HC11KTS/D